Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

Abstract: A wafer processing system including a processing chamber, a low pressure pump coupled to the processing chamber for pumping noble and non-noble gases, a valve mechanism coupling a source of noble gas to the processing chamber, an in situ getter pump disposed within the processing chamber which pumps certain non-noble gases during the flow of the noble gas into the chamber, and a processing mechanism for processing a wafer disposed within the processing chamber. Preferably, the in situ getter pump can be operated at a number of different temperatures to preferentially pump different species of gas at those temperatures. A gas analyzer is used to automatically control the temperature of the getter pump to control the species of gasses that are pumped from the chamber.

Abstract: Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

Abstract: Disclosed is a semiconductor layout design for use in integrated circuits that use balance circuitry. The semiconductor layout design includes a set of four substantially self enclosing gate transistors being arranged symmetrically about a common point. Wherein, each of the set of four substantially self enclosing gate transistors have a gate width that is defined by a perimeter around each of the set of four substantially self enclosing gate transistors. The semiconductor layout design preferably includes a balanced circuit having a set of first transistors and a set of second transistors. The set of first transistors being wired diagonally across the set of four substantially self enclosing gate transistors. In a preferred embodiment, the set of second transistors are wired diagonally across the set of four substantially self enclosing gate transistors in a manner that ensures that the set of second transistors are wired substantially perpendicular to the set of first transistors.

Abstract: A method for providing force feedback over a network supporting TCP/IP protocols by: (a) sending from a client computer over a network supporting TCP/IP protocols, a connection request to a web server connected to the network that is hosting a desired URL; (b) receiving and processing an HTML file at the client computer that was sent from the web server in response to the connection request, wherein the processing includes parsing an embedded force object reference having associated parameters and building a force object therefrom; (c) developing a force feedback signal with the force object; and (d) providing force feedback to a human/computer interface device coupled to the client computer in response to the force feedback signal.

Abstract: A process for producing a field emitter flat display includes providing a supported porous layer of a non-evaporable getter material by depositing the non-evaporable getter material on a substrate followed by sintering the deposited material. The substrate having the porous layer of non-evaporable getter material thereon is then housed in an inner space defined by opposing plates. The inner space is then evacuated and hermetically sealed. The non-evaporable getter material is preferably deposited by preparing a suspension of non-evaporable getter material particles in a suspending medium, coating a surface of a substrate with the suspension by, e.g., spraying, and sintering the coating.

Abstract: A mercury-dispensing device is disclosed that includes a mercury dispenser having the formula Ti.sub.x Zr.sub.y Hg.sub.z in which x and y are between 0 and 13, inclusive, the quantity x+y is between 3 and 13, inclusive, and z is 1 or 2; and a promoter that comprises copper, silicon and possibly a third metal selected among the transition elements. A getter material selected among titanium, zirconium, tantalum, niobium, vanadium and mixtures thereof, and alloys of these metals with nickel, iron or aluminum can be included in the device. The mercury dispense, promoter and optional getter material are provided preferably in the form of powders compressed as a pellet, or contained in a ring-shaped metallic support or rolled on the surfaces of a metallic strip. Also disclosed is a process for introducing mercury into electron tubes by making use of the above-mentioned mercury-dispensing devices.

Abstract: Disclosed is an apparatus and a method for spin coating chemicals over a surface of a substrate. The apparatus includes a bowl for supporting a substrate, the bowl has a plurality of drain holes defined below the level of the substrate. The apparatus further includes a lid having a flat surface configured to lie a predetermined distance above the substrate and mate with the bowl. Further, a plurality of injection holes defined in the bowl for applying a solvent to an underside of the substrate are included. The plurality of injection holes are defined in along an injection ring that is configured to receive the liquid solvent that is to be applied near an outer radius of the underside of the substrate, and the injection ring is spaced apart from the underside of the substrate.

Abstract: A getter pump module includes a number of getter disks provided with axial holes, and a heating element which extends through the holes to support and heat the getter disks. The getter disks are preferably solid, porous, sintered getter disks that are provided with a titanium hub that engages the heating element. A thermally isolating shield is provided to shield the getter disks from heat sources and heat sinks within the chamber, and to aid in the rapid regeneration of the getter disks. In certain embodiments of the present invention the heat shields are fixed, and in other embodiments the heat shield is movable. An embodiment of the present invention also provides for a rotating getter element to enhance getter material utilization.

Abstract: A method and apparatus for providing substantially pure hydrogen gas from a mixture of hydrogen and gaseous contaminants includes passing a gaseous mixture containing hydrogen gas and gaseous impurities through a purifier to form substantially pure hydrogen gas which is stored in a porous storage material including a getter material. The substantially pure hydrogen gas can be released from the porous storage matrix as desired. Preferably the purifier and porous storage matrix are separated by a thermally insulating matrix. The apparatuses can be combined in a serial configuration to provide a stream of substantially pure hydrogen gas at a substantially constant pressure.

Abstract: Disclosed is a method for amplifying a data signal read from a memory device. The method includes sensing an initial voltage difference across a data bus that is coupled to the memory device. Producing an initial voltage difference across a sensed data bus after the sensing detects the initial voltage difference. The initial voltage difference is configured to partially separate a pair of nodes associated with the sensed data bus. The method further includes subsequently isolating the data bus from the sensed data bus to rapidly further separate the pair of nodes associated with the sensed data bus, the rapid separation producing the amplified data signal across the sensed data bus.

Abstract: The present invention provides an interactive funnel amusement device. The interactive funnel amusement device allows a user to interact with the interactive funnel amusement device to a greater extent than prior art funnel devices. In one embodiment, the interactive funnel amusement device includes a funnel and a target. The target is located on an interior surface of the funnel such that when an object is rolled along the interior surface of the funnel the object is capable of interacting with the target. The interactive funnel amusement device can also include an adjustable guide. The adjustable guide is capable of guiding the object along one of a number of trajectories along the funnel such that the object rolls around the interior surface of the funnel in a substantially spiral manner. The adjustable guide can also be used to aim the object along a trajectory that causes the object to interact with the target located on the interior surface of the funnel.

Abstract: Disclosed is an apparatus for generating a memory access signal. The apparatus includes a latch having a set state for driving a set transistor, and a reset state for driving a reset transistor. The latch having an input terminal and an output terminal, and the latch transitions between the set and reset states in accordance with a system clock signal. The apparatus further includes a driver coupled to the output terminal of the latch for producing an access signal, and feedback path for feeding back the access signal to the input terminal of the latch. Wherein the latch operates to switch from the set state to the reset state in accordance with the fed back access signal. In this manner, the system clock is isolated from the set transistor when the latch is already in the set state.

Abstract: Low power consuming circuitry for amplifying sensed signals in memory devices is disclosed. The low power circuitry includes a amplifier circuit having a data bus line for receiving a data signal from a selected column of a memory array. The data bus line being coupled to a first pre-charger transistor for limiting a data bus voltage swing, and a virtual ground control line for controlling a virtual ground application to a selected column of the memory array. The virtual ground application configured to provide a path to ground for the selected column, and the virtual ground control line being coupled to a second pre-charger transistor for limiting a virtual ground voltage swing. Further included is a gain transistor configured to receive the data signal from the data bus line and provide an amplified data signal to a pull down node located at an input of an inverter. And, a digital data output node located at an output of the inverter.

Abstract: A method of removing an inorganic antireflective coating from a semiconductor substrate and a method of forming an integrated circuit (IC) are provided. In the former method, a sacrificial layer is formed over a semiconductor substrate, the layer being selectively removable from the substrate and compatible with photolithography. An inorganic antireflective coating such as SiON is then formed over the sacrificial layer. Thereafter, the sacrificial layer is removed from the substrate to lift the coating off the substrate. Preferred materials for the sacrificial layer include TiN, tetraethyl orthosilicate-based silicon oxide, spin-on-glass (SOG) such as hydrogen silsesquioxane and methyl silsesquioxane, and porous polymeric materials. In the latter method, a patterned layer of photoresist material is formed over the anitreflective coating.

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract: A method for forming a supported thin layer of non-evaporable getter (NEG) material and a getter device formed thereby are provided. A suspension comprised of non-evaporable getter (NEG) material particles in a dispersing medium is prepared. The NEG material particles in the suspension have a particle size not greater than about 150 .mu.m. The dispersing medium has an aqueous, alcoholic, or hydroalcoholic base and contains not more than about 1 wt % of organic compounds having a boiling temperature of at least about 250.degree. C. The ratio of the weight of the NEG material particles to the weight of the dispersing medium is between about 4:1 and about 1:1. A layer of the suspension is deposited on a carrier by a serigraphic technique. Next, the deposited layer is dried to evaporate volatile components of the dispersing medium and thereby form a dried deposit. Finally, the dried deposit is sintered under vacuum at a temperature between about 800.degree. C. and 1000.degree. C.

Abstract: Disclosed is an inventive multiple-chemistry etching method suited for etching through selected portions of layers in a layer stack in a plasma processing chamber. The layer stack preferably includes at least an anti-reflective layer and a metallization layer disposed below the anti-reflective layer. The method includes a first etching step where the anti-reflective layer of the layer stack is at least partially etched with a first chemistry, the first chemistry comprising an etchant chemical and a polymer-forming chemical. Once the first etching step is complete, the method proceeds to a second etching step where at least part of the metallization layer of the layer stack is etched with a second chemistry different from the first chemistry.

Abstract: A method and apparatus for providing a skill-based card game. A game apparatus displays cards on a display screen. The cards are provided from a deck to played by a player according to rules of the card game, where the player can make moves during the game with the drawn cards. A game score is based on the moves made by the player during the card game. The time duration in which the player makes the moves is recorded, and does not include time expired during the game in which moves cannot be made by the player. The game score is modified based on the time duration such that the less time expired during the moves, the greater the game score. The player can be penalized when the player fails to make a move when a move is possible. Also, equalized decks reduce the randomness of available moves during the card game. In one embodiment, the card game is similar to Solitaire, drawn cards are moved onto other cards in a display area as appropriate.

Abstract: Disclosed is a method of designing a memory device on a semiconductor chip. The memory device includes a memory array having a depth that defines a number of words and a word width that defines a number of bits. The method of designing the memory device includes partitioning an address transition detect circuit into a plurality of ATD sub-circuits. Partitioning a clock buffer into a plurality of clock buffer sub-circuits. Distributing each of the plurality of ATD sub-circuits to each of the number of bits of the memory array. The method of designing the memory device further includes distributing each of the plurality of clock buffer sub-circuits to each of the number of bits of the memory array. In a further variation, the method may be used to distribute the ATD sub-circuits and the clock buffer sub-circuits to where the clock load is distributed for a particular memory device.