Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer.

Abstract: Disclosed is an operational amplifier having a positive input terminal, a negative input terminal, an output terminal, a positive power supply input and a negative power supply input. The operational amplifier includes a transistor input pair being coupled to the positive input terminal and the negative input terminal. A first charge pump being coupled to positive supply circuitry contained within the operational amplifier. The first charge pump being configured to operate the positive supply circuitry contained within the operational amplifier at an enhanced positive power supply. The operational amplifier further includes a second charge pump being coupled to negative supply circuitry contained within the operational amplifier. The second charge pump being configured to operate the negative circuitry contained within the operational amplifier at an enhanced negative power supply. Accordingly, the transistor output pair provides an essentially full rail-to-rail output.

Abstract: A process is disclosed for producing non-evaporable getter materials having high porosity and improved gas absorption rates. The process includes mixing together a metallic getter element, a getter alloy and a solid organic compound, all three components being in the form of powders having specific particle sizes. The mixture is subjected to a compression of less than about 1000 kg/cm.sup.2 and is sintered at a temperature between about 900.degree. C. and about 1200.degree. C. for a period between about 5 minutes and about 60 minutes. The getter material thus obtained is used to produce getter bodies shaped as pellets, sheets or discs having better mechanical strength than similar bodies of other getter material having comparable porosity.

Abstract: An embedded memory device structure, and a method for making the embedded memory device structure having self adjusting pre-charge delay characteristics. The method includes selecting a desired memory array having a dummy column of cells. Coupling a pre-charge detect circuit to the dummy column of cells. The pre-charge detect circuit is configured to measure an activation and pre-charge response time of cells contained within the dummy column of cells. Transferring the activation and pre-charge response time to an address transition detect unit. The method further includes generating a custom clock timing signal in response to the activation and pre-charge response time of cells contained within the dummy column of cells.

Abstract: A wafer processing system including a processing chamber, a low pressure pump coupled to the processing chamber for pumping noble and non-noble gases, a valve mechanism coupling a source of noble gas to the processing chamber, an in situ getter pump disposed within the processing chamber which pumps certain non-noble gases during the flow of the noble gas into the chamber, and a processing mechanism for processing a wafer disposed within the processing chamber. Preferably, the in situ getter pump can be operated at a number of different temperatures to preferentially pump different species of gas at those temperatures. A gas analyzer is used to automatically control the temperature of the getter pump to control the species of gasses that are pumped from the chamber.

Abstract: A method for fabricating chip size packages which uses a lamination process, thereby not only achieving an improvement in the reliability of final electronic products, a reduction in the manufacturing costs, and a mass production resulting in a high marketability, but also being applicable to the fabrication of packages for both memory and non-memory chips and enabling the final electronic products to have high electronic performance while making the package size of the final electronic products not greater than 1.2 times the semiconductor chip size.

Abstract: A mercury-dispensing device is disclosed that includes a mercury dispenser comprising an intermetallic compound including mercury and a second metal selected from the group consisting of titanium, zirconium, and mixtures thereof; and a promoter that comprises copper, tin and at least a third metal selected among the rare earth elements. A getter material selected among titanium, zirconium, tantalum, niobium, vanadium and mixtures thereof, and alloys of these metals with nickel, iron or aluminum can be included in the device. The mercury dispenser, promoter and optional getter material are provided preferably in the form of powders compressed as a pellet, or contained in a ring-shaped metallic support or rolled on the surfaces of a metallic strip. Also disclosed is a process for introducing mercury into electron tubes by making use of the above-mentioned mercury-dispensing devices.

Abstract: Disclosed is a method and apparatus for designing re-useable interfacing logic hardware shells which provide interface functions between a hardware core and one or more busses. An interface logic hardware shell provides previously characterized, tested and implemented interface logic designs for use in future applications with little or no redesign. The hardware circuitry (cells) of which such shells are comprised includes circuitry for bus interface units, memory interface units, buffers, and bus protocol logic. The cores for which the shells provide interface functions include CPU cores, memory cores, digital video decoding cores, digital audio decoding cores, ATM cores, Ethernet cores, JPEG cores and other data processing cores.

Abstract: A DV codec process for reduced-quality size decoding of DV encoded video data receives a DV encoded bit stream. Compressed macroblock information and DCT information, including a DC coefficient value, is read for a current DCT block. It is determined whether the current DCT block is a still DCT block. If the current DCT block is a still DCT block, run length decoding is performed to obtain a number of low frequency AC coefficient values for the current still DCT block and a reduced coefficient inverse discrete cosine transform is performed on the low frequency AC coefficient values to yield decoded pixel values for the current still DCT block. If the current DCT block is a motion DCT block, run length decoding is performed to obtain a number of low frequency AC coefficient values for the current motion DCT block and a reduced coefficient inverse discrete cosine transform is performed on the low frequency AC coefficient values to yield decoded pixel values for the current motion DCT block.

Abstract: The invention provides a three dimensional digital scanner which includes a multiple view detector which is responsive to a broad spectrum of visible light. The multiple view detector is operative to develop a plurality of images of a three dimensional object which is being scanned. The plurality of images are taken from a plurality of relative angles with respect to the object, and the plurality of images depict a plurality of surface portions of the object. A digital processor including a computational unit is coupled to the detector and is responsive to the plurality of images so that it develops 3-D coordinate positions and related image information for the plurality of surface portions of the object. A three dimensional image of the object to be scanned is thus developed by the digital processor. The data developed includes both shape and surface image color information.

Abstract: An arcade game including an object sensor for detecting a playing piece directed by a player. A target field including at least one target receives the directed playing piece, and the sensor determines the identity and a position of the playing piece. A scoring mechanism provides a game score based on a distance between the final resting position of the playing piece and one of the targets. In a described embodiment, the playing piece is a golf ball putted by the player toward a target hole. A removal mechanism removes the playing piece from the target field so that the player may retrieve the playing piece. The sensor includes a visual sensor, such as a video camera, and a digital processor for examining recorded images of the target field to validate the playing piece, determine a final position of the playing piece, and determine the distance between the playing piece and the target. Target field images can also be examined to determine and validate the trajectory of the playing piece.

Abstract: A method of improving the planarity of spin-on-glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces in a trace layer that exceed a predetermined distance are provided with dummy lines having a specific geometry in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined distance is greater than approximately 1 micrometer, as for example in the range of approximately 3 to 6 micrometers. In some applications, both the active conductive traces and the dummy lines are formed from a metallic material that is deposited in one single step with a passivation layer being deposited over both the conductive traces and the raised lines prior to application of the spin-on glass layer.

Abstract: A combination cryopump/getter pump including a cryopump section having a cryopump inlet, a getter pump section having a getter pump inlet, and a mechanism for coupling the cryopump section and the getter pump section to a single port of a process chamber to be evacuated. Preferably, a cylindrical cryopump section surrounds a cylindrical getter pump section. Preferably, the cryopump section and the getter pump section are coupled to the common port of the process chamber by a gate valve mechanism. In one embodiment of the present invention, the gate valve mechanism isolates the cryopump inlet and the getter pump inlet when in a closed position, and in another embodiment of the present invention the gate valve does not isolate the cryopump inlet from the getter pump inlet when in a closed position. Preferably, thermal insulation is provided between the getter pump section and the cryopump section to thermally isolate the two sections. The cryopump section preferably includes both a 15.degree. K array and a 80.

Abstract: An improved vacuum crane game and method. Multiple prizes are provided on a rotating turntable. A player may control horizontal movement of a vacuum pick-up device positioned above the prize area. The pick up device includes a vacuum head that may be raised and lowered relative to the turntable in a z-direction. The vacuum head is used to pick up one of the prizes using a suction force that is provided by a vacuum pump coupled to the vacuum head by a hose and located away from the vacuum head. In one embodiment, a vacuum sensor in the vacuum head may sense whether a prize is picked up. The pick-up device is moved to a dispenser area and the suction force is removed to allow the prize to fall to a conveyor device, which moves the prize to a dispenser where it is delivered to the player.

Abstract: A method of improving the planarity of spin-on glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces on a trace layer of a semiconductor wafer that exceed a predetermined threshold distance are provided with dummy surfaces arranged in a micro-pattern in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined threshold distance is greater than approximately 2 micrometers, as for example in the range of approximately 4.65 to 5 micrometers. In some applications, both the active conductive traces and the dummy surfaces are formed from a metallic material that is deposited in one single step with a dielectric layer being deposited over both the active conductive traces and the dummy surfaces prior to application of the spin-on glass layer.

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract: An improved ESD cell provides in the worst case 2,000 volts HBM ESD protection using an NMOS transistor in a lightly-doped drain process. An NMOS transistor has its source connected to ground, and its drain connected through a polysilicon resistor to a pad of an integrated circuit. The pad is also connected by metal to an n+ pocket tap of an n-type epitaxial layer formed on a p-type substrate. The connection of pad metal to the pocket tap forms a second parasitic lateral bipolar junction transistor (BJT) having as a base the p-type well, having an emitter the source of the NMOS transistor, and having as its collector the pocket tap. The parasitic transistor turns on at the right moment and is able to shunt more current around the polysilicon resistor, thus giving a dramatic increase in ESD protection. In a worst case, the ESD cell can pass at a minimum of 2,000 volts, and the expected range of HBM ESD values is between 2,500 volts and 3,000 volts depending upon process variations.

Abstract: A reusable hardware layout ("core") for performing some, but not all, MPEG and AC-3 audio decoding functions. Specifically, the audio core performs matrixing and windowing operations of MPEG and AC-3 decoding. The disclosed audio core design includes a data path, a control logic unit, an input RAM interface (for controlling an input RAM), an output RAM interface (for controlling an output RAM), a ROM, a ROM addressing logic unit, and a registers interface. The input RAM and the output RAM are located outside of the audio core. The control logic unit specifies in which state of multiple states the audio core currently resides, with each of the multiple states specifying one function or group of functions of either the MPEG or AC-3 decoding process. The control logic unit includes an MPEG state machine for generating MPEG state and cycle count information and an AC-3 state machine for generating AC-3 state and cycle count information.

Abstract: Disclosed is a spinning chemical applicator for spin coating a work piece. The spinning chemical applicator includes a bowl having a base region and substantially curved walls. A chuck base having a chuck plate for holding the work piece, the chuck base and the chuck plate contained within an inner region of the bowl. A bowl covering lid being mounted on a top surface of the substantially curved walls. A plurality of upper venting holes being defined in the substantially curved walls, the plurality of upper venting holes defining a venting path to the inner region of the bowl. And plurality of venting drain holes defined in the substantially curved walls at an edge location that is substantially below each of the plurality of upper venting holes. The plurality of venting drain holes providing a venting and drain path for the inner region of the bowl.