Abstract: A communications system includes a vector modulator controller receiving a data stream and developing a vector modulator control signal by GMSK waveform synthesis and a transmitter having a vector portion controlled by the vector modulator control signal. The vector modulator controller includes: (1) ROM memory storing a plurality of waveform maps including an alternating map, a constant map, a monotonic sine map, and a monotonic cosine map; (2) a counter coupled to the ROM memory and capable of developing a sequence of ROM addresses; (3) a temporal bit generator responsive to a data stream, the temporal bit generator developing a next bit Nb, a current bit Cb, and a past bit Pb from the data stream; (4) control circuitry to develop a digital waveform signal from selected waveform maps in the ROM memory; and (5) a pair of DACs responsive to the digital waveform signal and operative to output a vector modulator control signal that encodes the data stream.

Abstract: A laser diode driver with automatic power control in which start-up characteristics are controlled to avoid unsafe power levels at a driven laser is disclosed. The laser diode driver according to the invention produces a bias control signal that controls a bias current source such that the bias current supplied to the laser is maintained below a predetermined level during a start-up period.

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and nonsacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer.

Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

Abstract: A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.

Abstract: The present invention is directed at prioritizing and interleaving data transfer protocols between storage mediums and main memories. The invention includes a controller interface that is operatively connected to a plurality of storage mediums, a main memory and a central processing unit (CPU). The controller interface is preferably configured to receive and detect data transfer protocol requests having different timing parameters. Once the controller interface receives a data transfer protocol request, an arbitration unit that is operatively coupled to said controller interface assigns priorities to the detected data transfer protocols having different timing parameters. The arbitration unit then compares the assigned priorities, and interrupts an on-going data transfer protocol when a newly received data transfer protocol is assigned a higher priority. The data transfer protocol assigned the high priority is then commenced and proceeds to completion.

Abstract: A phase locked loop including a comparator, a VCO controller, and a VCO having a multi-stage oscillator portion and a combinational logic portion. The comparator is responsive to an input clock and a VCO comparison clock and is operative to produce a comparator output signal. The VCO controller is responsive to the comparator output signal and is operative to produce a VCO control signal. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of the VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency.

Abstract: A distance measuring apparatus according to the present invention comprises two types of distance measuring units, which are a first distance measuring unit of the active method for receiving reflected light of measuring light returning from an object and performing distance measurement based on a focused position thereof, and a second distance measuring unit of the passive method for receiving the natural light reflected by the object through two optical systems and performing the distance measurement based on two optical images thus obtained. The apparatus further has a luminance determining unit for determining a luminance of the external field from a photometry result, and a distance selecting device for selecting and outputting either one of distance measurement results obtained by the first distance measuring unit and second distance measuring unit as a proper distance value, based on the luminance of the external field determined by the luminance determining unit.

Abstract: An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

Abstract: An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first reduced from the prior art cell heights, and the width of the cell is then varied according to the particular need of the circuit. When the drive strength of the I/O circuit is high, and the circuit is more complicated, a wider cell is assigned. Conversely, for a circuit that is relatively simple, a narrower cell will be assigned. Each I/O cell has one associated bonding pad which is placed directly below the starting point of that cell. The height of the cells may also be varied on each side of the chip in order to be able to place more I/O cells along one or more sides or edges of the chip.

Abstract: A compact getter pump, compatible with size limitations of portable apparatus is described. In one embodiment a getter device and a heating apparatus capable of heating getter elements to a desired temperature, are contained within a thermally insulating housing comprised of a plurality of nested thermally insulating shields with an open end. The open end of at least one of the shields is covered with a particle trap. In another embodiment, each of the nested thermally insulating shields is of a substantially cylindrical shape and is substantially coaxially disposed along an axis defined by the heating apparatus. In one embodiment a plurality of getter elements and a heating apparatus are enclosed by three nested evenly spaced cylindrical metal shields that have open ends and are coaxially disposed along an axis defined by the getter elements and the heating apparatus.

Abstract: A coating apparatus for detecting the presence of contaminants carried by a liquid a is that is applied as a coating on a workpiece. A tube guides the liquid along a flow path to the workpiece. A light source illuminates the liquid along the flow path with an optical fiber or other light carrier, and light is scattered by any contaminants present in the liquid. Light scattered by the contaminant particles is more intense than light scattered by the other liquid particles, and this brighter scattered light is detected by a light detector positioned adjacent to the fluid flow path. The coating system is particularly well suited for use in a spin-on coating process that applies a liquid, such as a photoresist material or a dielectric material, to a semiconductor wafer or other workpiece that is secured to a rotating turntable and rotated to receive a coating of the liquid.

Abstract: A RAM and I/O controller is provided with logic for controlling access to a DRAM and to one or more input and/or output latches, each of which are coupled to a RAM data bus. The logic receives input signals such as a refresh request signal and a RAM access request signal from other circuits or devices, and outputs one or more associated control signals onto a RAM control bus, such as a RAS output signal or a CAS output signal. The logic includes at least one idle state during which the DRAM is in a RAS or CAS precharge period. During the idle state, the logic de-asserts the RAS or CAS output and asserts one or more control signals to the input and/or output latches so as to perform at least one write and/or read operation of miscellaneous data signals with the latches 112 and 114 of FIG. 2a over the temporarily idle RAM data bus.

Abstract: A gate array masterslice having a minimal input/output slot and variable pad pitch architecture is disclosed. In the masterslice, many identical input/output slots ring the periphery of a semiconductor substrate and contain only the special devices necessary for input/output circuits. Each of the input/output slots include (i) a first region containing a plurality of tuning transistors of different sizes, (ii) a second region having one or more PMOS transistors, each of a size greater than any one of the plurality of tuning transistors, (iii) a third region having one or more NMOS transistors, each of a size greater than any one of the plurality of tuning transistors, and (iv) a fourth region containing one or more devices for providing electrostatic discharge protection. One to four PMOS transistors are provided in the second slot region and one to four NMOS transistors are provided in the third slot region.

Abstract: A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are configured to operate concurrently and asynchronously. The bridge circuit includes a host master circuit and a PCI slave circuit coupled between the host bus and the PCI bus and configured to service a PCI-MEMORY instruction from an external PCI master coupled to the PCI bus. A PCI master circuit and a host slave circuit within the bridge circuit couples between the PCI bus and the host bus and configured to service a CPU-PCI transaction from a CPU coupled to the host bus. The aforementioned deadlock condition occurs when the PCI-MEMORY transaction proceeds simultaneous with an issuance of the CPU-PCI transaction. The deadlock detection and resolution circuit includes first circuit for asserting an asynchronous handshake signal to the PCI slave of the bridge circuit.

Abstract: Disclosed is a method for programming an antifuse structure. The antifuse structure is programmed by applying an alternating current having alternating current pulses between a bottom and a top electrode to generate a conduction path through an antifuse material sandwiched between the electrodes. The conduction path is formed incrementally due to an electron flow produced as a result of each alternating current pulse thereby defining the conduction path at a substantially centered portion of the antifuse material.

Abstract: Disclosed is a method for making a shallow trench structure in a semiconductor substrate. The method includes: (a) forming a mask over a semiconductor substrate, the mask being provided with an aperture extending therethrough which exposes a region of the semiconductor substrate, the aperture having substantially vertical sidewalls; (b) depositing a blanket of silicon over the mask and within the aperture; (c) anisotropically etching the deposited silicon to form temporary spacers having curved profiles at the sidewalls of the aperture, the temporary spacers transferring the curved profiles to a mouth of a shallow trench being etched at the region of the semiconductor substrate as the temporary spacers are etched away; (d) whereby a shallow trench structure is formed where the mouth has a curved profile.

Abstract: Disclosed is a latch sense amplifier output buffer for amplifying a data signal read from a memory. The latch sense amplifier output buffer includes a sense amplifier core having an amplifier circuit. The amplifier circuit provides amplification on the data signal read from a random access memory cell location. The sense amplifier core is preferably configured to generate an amplified data signal. Further included is an output data latching circuit that is configured to substantially simultaneously store the amplified data signal and generate an output data signal. An output buffer core includes an output driver circuit having a pull up transistor and a pull down transistor. The output driver circuit substantially concurrently receives the amplified data signal from the sense amplifier core and the output data signal from the output data latching circuit.

Abstract: An arcade game including a progressive bonus apparatus connected to a plurality of individual game units. The progressive bonus apparatus receives score contributions from each game unit to increase a progressive score. When players achieve a predetermined task on a game unit, they receive a non-monetary award based on the progressive score. Each game unit connected to the progressive bonus apparatus may take the form of an arcade-type game with a rotating wheel on which to base scoring. A playing piece is directed down a playing surface towards a target end, and the wheel is rotated according to the target that was hit by the playing piece. The position of the wheel when it stops rotating affects the score. A non-monetary award based on the score is dispensed to the player when the game is completed.