Abstract: The present disclosure relates to mass storage devices and, more particularly, to transferring data between mass storage devices.

Abstract: In one embodiment, an apparatus is described. The apparatus includes an input/output (I/O) device that is capable of being coupled to a computing system. The device is configured such that, in operation, the I/O device has the capability to interrupt an associated computing system processor based at least in part on a comparison of a threshold value with the quantity of transmit resources available to the I/O device.

Abstract: Briefly, in accordance with one embodiment on the invention, a method of compressing a data set includes the following. In multiple passes, each data signal in the data set is categorized into a category of a predetermined set, and, for selected categories of the predetermined set, the data signals for that category are coded using a codebook for that category. Briefly, in accordance with another embodiment of the invention, a method of decompressing a compressed data set includes the following. For compressed data signals in the data set in one category of a predetermined set of categories, a signal associated with the particular category is employed for the compressed data signal, and, for selected categories of the predetermined set, the compressed data signals for that category are decoded using a codebook for that category.

Abstract: Briefly, in accordance with one embodiment a bridge circuit for use in a computing platform includes a plurality of signal ports. At least one of the plurality of signal ports is adapted to be coupled to a long haul interface. At least one of the plurality of signal ports is adapted to be coupled to a host interface. At least one of the plurality of signal ports is adapted to be coupled to a short haul interface. The bridge circuit is adapted to provide a bridge between the host interface and one of the short haul interface and the long haul interface. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: Embodiments of a method of generating Huffman code length information are disclosed. In one such embodiment, a data structure is employed, although, of course, the invention is not limited in scope to the particular embodiments disclosed.

Abstract: A circuit including a plurality of latches including feedback control circuitry and a plurality of data input terminals and data output terminals respectively coupled to alternative sides of said plurality of latches.

Abstract: In accordance with one embodiment of the invention, a method is provided for integrating at least a portion of a watermark into at least a portion of a compressed image. The method of this embodiment includes encoding at least a portion of the watermark and compressing at least a portion of the image. The encoded watermark, or portion thereof, and the compressed image, or portion thereof, are combined. Of course, many other embodiments in accordance with the invention are included within the scope of the present invention.

Abstract: Embodiments are disclosed that include a low power memory and/or a low power data path. One particular embodiment, for example, includes a technique to reduce power consumption. In one particular embodiment, for example, a grouping of bits, such as a 32-bit word, for example, is stored in inverted form if more than half of the bits have a bit value of logic “1” rather than logic “0.” Likewise, in this embodiment, if more than half of the bits have a bit value of logic “0” rather than logic “1,” then the grouping of bits is not stored in inverted form.

Abstract: In accordance with one embodiment of the invention a circuit includes a split delay-chain, a phase detector, and a voltage controlled oscillator (VCO) coupled so as to produce a clock signal based on a non-external reference.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of updating BIOS using an externally provided module may include the following. In this context, the term externally provided means that the module resides in a device other than that used to hold the firmware code, such as a magnetic storage device, typically with a lower cost per bit of information. In this embodiment, the BIOS, while in control of or being executed by a processor, applies a one-way hash process to a portion of the externally provided module. The computed hash of the module portion is compared with the pre-computed hash value included with the BIOS code. The external module is then invoked as a subprogram if and only if the hash values compare as equal. The module, while executing, may then validate the remainder of the update using more sophisticated cryptographic techniques and/or perform the update directly.

Abstract: Embodiments of a method of performing Huffman decoding are disclosed. In one such embodiment, a data structure is employed, although, of course, the invention is not limited in scope to the particular embodiments disclosed.

Abstract: Briefly, in accordance with one embodiment of the invention, a power brick for use with a network adapter includes: a power supply and at least one signal transformer. The power supply and the signal transformer are physically remote from the network adapter and capable of being electronically coupled to the network adapter via a cable.

Abstract: Briefly, in accordance with one embodiment of the invention, a circuit includes: a physical arrangement of power transistors. The circuit is adapted to couple a node to a power bus segment. The physical arrangement of power transistors is electronically configurable, based on externally derived electrical signals, to sink power to the node from the power bus segment, source power from the node to the power bus segment, and distribute power through the node.

Abstract: Briefly, in accordance with one embodiment of the invention, a node includes: a circuit. The circuit is configurable based, at least in part, on control signals external to the node to be applied to the node via a power distribution system formed when the node is coupled to a plurality of nodes. The circuit includes the capability to deliver and to interrupt the delivery of power via the power distribution system.

Abstract: Various methods of caching web resources include caching in accordance with a number of times accessed, a frequency of access, or a duration of access. One method of caching web resources includes the step of accessing a first web resource. The first web resource is cached, if no other web resource is accessed after a pre-determined period of time. Another method of caching web resources includes the step of accessing a first web resource. The first web resource is cached, if the first web resource is subsequently accessed more than a pre-determined number of times. Another method of caching web resources includes the step of accessing a plurality of web resources. The accessed web resources are cached as cached web resources in accordance with at least one of a number of times accessed, a frequency of access, or a duration of access. An apparatus comprises storage media containing caching logic for caching web resources.

Abstract: Briefly, in accordance with one embodiment of the invention, a DC-to-DC converter includes: a synchronous rectifier converter. The synchronous rectifier converter includes a buck converter. The transformer of the synchronous rectifier converter employs less than five windings on the secondary.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide circuit configurations. The output buffer is adapted to couple to separate voltage supply voltage level ports and is further adapted to switch between the circuit configurations. The respective circuit configurations are respectively specifically adapted for interoperating with other integrated circuit chips, the respective threshold voltage levels of the semiconductor devices of different other integrated circuit chips being different.

Abstract: A resistive capacitive timer scheme is described. Specifically, the invention includes a circuit to compensate for a leakage current through a capacitor in the resistive capacitive timer.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.

Abstract: Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled.