Abstract: Briefly, in accordance with one embodiment of the invention, a complementary metal-oxide semiconductor (CMOS) integrated circuit includes: a CMOS image sensor. The integrated circuit further includes an analog-to-digital (A/D) converter, at least one analog signal storage circuit, and control circuitry to multiplex the application of signals to the A/D converter from the image sensor and the at least one analog signal storage circuit.

Abstract: Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance. Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance of an interface circuit output buffer comprises: digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance, and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.

Abstract: Briefly, in accordance with one embodiment, an integrated circuit includes a circuit to produce discrete output signals that include a multilevel, data dependent voltage bias level, wherein the circuit further includes the capability to at least approximately cancel a zero introduced in the frequency response of the circuit due to capacitive coupling. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes at least one comparator coupled to compare input and output voltage signal levels. The integrated circuit further includes circuitry to signal for an adjustment in the output voltage signal levels based, at least in part, on the computer output signal.

Abstract: Briefly, in accordance with one embodiment of the invention, a slew rate control circuit for a processor includes: a circuit configuration to produce a signal representing the speed of fabricated transistors; and a circuit configuration to adjust, based at least in part on the signal representing the speed of fabricated transistors, the amount of current produced by a pre-driver stage for an output buffer of the processor. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a slew rate control circuit for a buffer including: a register capable of storing at least one binary digital signal, a pre-driver, and at least one pre-driver cell coupled to the pre-driver. The at least one pre-driver cell is coupled to the pre-driver and register so as to modify the amount of current produced by the pre-driver based, at least in part, on the at least one binary digital signal.

Abstract: A DC-to-DC converter includes: a first and a second inductor path, the inductor paths being coupled in the converter so as to provide a single voltage output signal during converter operation. An array of switches are coupled so as to control the application of voltage sources to the inductor paths during converter operation. The switches and the array are coupled so that their states are controlled, at least in part, based upon the voltage signal level of the single voltage output signal during converter operation.A method of producing a voltage signal is as follows. One of two voltage sources is applied to an inductor circuit to produce an output voltage signal. The voltage source supplied is switched based, at least in part, on the voltage signal level of the output voltage signal.

Abstract: An integrated circuit includes: a comparator coupled in a configuration to compare two voltages. One of the two voltages includes a semiconductor junction voltage drop. The other of the two voltages includes a voltage signal, X V.sub.t, where V.sub.t is a thermal voltage and X includes a selected signal value, which modulates the thermal voltage. The configuration includes a feedback path to vary X until X V.sub.t approximately equals the voltage including the semiconductor junction voltage drop.

Abstract: Briefly, in accordance with one embodiment of the invention, a circuit includes a DC-to-DC converter. The DC-to-DC converter includes a high-side field effect transistor (FET) and FET driver. The gate of the high-side FET is AC coupled to the FET driver. The gate-to-source electrical path of the high-side FET is coupled to be driven by a substantially fixed voltage during circuit operation.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of transmitting coded data signals over a bus having a limited bandwidth includes: transmitting a first edge of a data pulse and transmitting a second edge of the data pulse. The time period between the transmitted first edge and the transmitted second edge approximates one of a set of different predetermined time periods. Selected different predetermined time periods of the set of different predetermined time periods respectively correspond to unique pluralities of binary digital signals.Briefly, in accordance with another embodiment of the invention, a system comprises a first device, a second device and a bandlimited bus coupling the first device with the second device. At least one of the devices includes the capability to code data signals for transfer over the bus and at least the other device includes the capability to decode the data signals.

Abstract: A voltage overshoot protection circuit includes an integration circuit configuration. The integration circuit configuration is included in the voltage overshoot protection circuit so as to integrate excess diverted current drawn from a bus. The voltage overshoot protection circuit is adapted to be electrically coupled to the bus.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a latching sense amp circuit. The latching sense amp circuit is configured in the integrated circuit so that the signals to produce and latch an output signal consist essentially of a precharge pulse and a capture pulse.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a phase frequency detector (PFD) including two clock input ports, an up signal output port, and a down signal output port. The PFD includes digital circuitry including transistors coupled in a configuration to adjust an amount of overlap of an up signal and a down signal based, at least in part, upon the magnitude of an amount of phase delay between two clock signals respectively applied to the PFD input ports. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a phase frequency detector (PFD) including two clock input ports, an up signal output port, and a down signal output port.

Abstract: Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of using a bypass buffer in a node coupled to a ringlet includes the steps of: writing a packet of binary digital signals on the ringlet into the bypass buffer; and retaining the packet of binary digital signals in the bypass buffer for a predetermined amount of time before transferring the packet to the ringlet.Briefly, in accordance with another embodiment, a node to be coupled to a ringlet includes: a transmit buffer and a receive buffer. The transmit and receive buffers are coupled in a configuration to transfer binary digital signals between the node and the ringlet via the transmit and receive buffers. The configuration further includes a bypass buffer to temporarily queue binary digital signals passing through the node. The bypass buffer is further coupled in the configuration to retain a packet of binary digital signals for a predetermined amount of time before transferring the packet to the ringlet.

Abstract: Briefly, in accordance with one embodiment of the invention, a coarse frequency burst detector for use at the receiving end of a wireline communications system comprises: a digital signal filter adapted to filter a component of decoded signal samples, the decoded signal samples being derived from a baseband signal transmitted via the wireline communications system; and a threshold detector adapted to threshold the signal level of the filtered component of the decoded signal samples with respect to a substantially predetermined level. In accordance with another embodiment, a method of detecting at the receiving end of a wireline communications system a frequency burst in a baseband signal transmitted via the wireline communications system comprises the steps of: filtering a component of a decoded signal derived from the baseband signal transmitted via the wireline communications system; and thresholding the filtered component.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of compensating for Doppler error in a wireless communications system employing Viterbi decoding comprises the steps of: for each signal sample in a first predetermined-sized grouping of received signal samples, performing a parallel Viterbi update and short symbol decode; and for a second predetermined-sized grouping, forming by pipeline processing an estimate of the Doppler error in accordance with the parallel short traceback decoding performed for the first grouping, and adjusting each signal sample in the second grouping in accordance with the estimated Doppler error.Briefly, in accordance with another embodiment of the invention, a Viterbi traceback reconstructed signal sample index comprises: a state counter, a traceback shift register (TBSR); a signal reconstruction table; and a comparator coupled in a configuration so as to provide the sign bit to the TBSR from a comparison of binary digital signals.

Abstract: A line driver having two halves arranged in a push-pull configuration. Each half has a pass transistor, connected between a power supply rail and an output terminal, and an amplifier with an output coupled to the output terminal. Only one of the pass transistors conducts at any given time. A sense transistor, coupled between the power supply rail and the input of the amplifier, varies the output of the amplifier to compensate for variations in the conductivity of the conducting pass transistor. Preferably, the current density in the sense transistor is substantially the same as in the conducting pass transistor.

Abstract: An electronically-controlled variable propagation delay digital signal inverter comprises a digital signal inverter having an input signal port and an output signal port, and an electronically-controlled negative resistance (ECNR). The ECNR is coupled to the output port of the inverter in a configuration so as to render the propagation delay of the digital signal inverter capable of being varied by varying the resistance of the ECNR. The electronically-controlled variable propagation delay digital signal inverter may be included in a ring oscillator configuration.

Abstract: Briefly, in accordance with one embodiment of the invention, an extendible local area network includes a hub station including a memory and at least one hub station segment. The hub station segment is adapted to be coupled to at least N other hub station segments by a bi-directional control signal bus, N being a positive integer. The hub station segment includes at least two ports, each of the ports being adapted to receive electrical signal packet transmissions from a remote station. The memory and the hub station segment are mutually coupled by a signal bus.

Abstract: An extendible, round robin, local area hub station network includes: at least two round robin hub station segments coupled so as to form a ring-shaped hub station segment signal path. One of the two hub station segments includes a master hub station segment adapted to provide control signals, such as electrical or optical signals, on the ring-shaped segment signal path to transfer control of round robin polling over the hub station network between any two hub station segments in the hub station network. The hub station segments are also mutually coupled by a signal bus.

Abstract: Briefly, in accordance with one embodiment of the invention, an electrical circuit comprises: a digital-controlled oscillator. The digital-controlled oscillator includes an edge delay oscillator being adapted to produce digital oscillator pulses in response to digital clock pulses, each of the oscillator pulses having a rising edge and a falling edge. The edge delay oscillator is further adapted to delay at least one of the oscillator pulse edges in response to a delay signal. In accordance with another embodiment of the invention, an electrical circuit comprises: a digital-controlled oscillator, the oscillator including a clock having a substantially predetermined frequency. The oscillator is adapted to produce a digital output signal comprising a series of digital output pulses.