Abstract: Briefly, in accordance with one embodiment of the invention, a method of forming at least two vias, each having a metal overlap, to interconnect at least two connection points with metallization includes the following. The at least two vias are etched through a layer of insulating material. The at least two etched vias are located diagonally with respect to one another. Metal overlap for each of the at least two vias is formed into a polygon shape having more than four sides. Briefly, in accordance with another embodiment of the invention, an article includes: a storage medium, the storage medium having stored thereon, instructions, which, when executed, result in: the placement and routing of vias between at least two connection points to be interconnected with metallization by positioning at least two vias diagonally with respect to one another, the at least two vias being positioned so each is capable of having a polygon shape of metal overlap with more than four sides.

Abstract: A circuit including a plurality of latches including feedback control circuitry and a plurality of data input terminals and data output terminals respectively coupled to alternative sides of said plurality of latches.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes a bias voltage source. The bias voltage source is coupled to a pad of the integrated circuit so as to clamp the pad voltage to the bias voltage when, during circuit operation, the voltage of the pad exceeds an upper voltage rail of the integrated circuit.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Abstract: Briefly, in accordance with one embodiment of the invention, a DC-to-DC converter includes: a circuit configuration to modify the set point of the output voltage signal level of the DC-to-DC converter circuit in response to a transient signal by an amount related, at least in part, to the magnitude of the transient signal. Briefly, in accordance with yet another embodiment of the invention, a DC-to-DC converter circuit includes: a high-side and a low-side voltage switching device. The switching devices are coupled in a circuit configuration to apply a control voltage signal to each switching device based, at least in part, on the state of the other switching device.

Abstract: An integrated circuit includes logic to process a received transport-protocol compliant packet. The logic is adapted to forward at least some portions of the packet so that the portions will be transmitted along an auxiliary bus. The portions are forwarded based, at least in part, on specific binary digital signals being provided in fixed, predetermined locations in the packet.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of performing high speed signaling includes the following. A preamble signal and an end of packet (EOP) signal are transmitted at a low frequency using rail-to-rail voltage signal levels. Later, high frequency signaling is transmitted using a voltage signal level swing that is less than rail-to-rail.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a stress-follower circuit configuration. The stress-follower circuit of the configuration is coupled to a pad of the integrated circuit. The stress-follower circuit configuration is coupled so as to reduce the voltage stress on the gate of a transistor in a transistor stack so that in operation the transistor in the stack tolerates an operating voltage approximately 1.5 volts above its nominal voltage. The transistor stack is also coupled to the pad.

Abstract: Briefly, in accordance with one embodiment, an integrated circuit includes a circuit to produce discrete output signals that include a multilevel, data dependent voltage bias level, wherein the circuit further includes the capability to at least approximately cancel a zero introduced in the frequency response of the circuit due to capacitive coupling. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes at least one comparator coupled to compare input and output voltage signal levels. The integrated circuit further includes circuitry to signal for an adjustment in the output voltage signal levels based, at least in part, on the comparator output signal.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a flicker filter circuit. The flicker filter circuit has a configuration so that during filter operation two line buffers are employed to store partial sums of the filtered input digital signal samples. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: three line buffers, three multipliers, and three adders. The buffers, multipliers and adders are coupled in a circuit configuration so as to implement a flicker filter during circuit operation.

Abstract: Briefly, in accordance with one embodiment of the invention, a power brick for use with a network adapter includes: a power supply and at least one signal transformer. The power supply and the signal transformer are physically remote from the network adapter and capable of being electronically coupled to the network adapter via a cable. Briefly, in accordance with another embodiment of the invention, a power brick for use with a network adapter includes: at least two signal transformers. The at least two signal transformers are physically remote from the network adapter and capable of being electronically coupled to the network adapter via a cable. Briefly, in accordance with on more embodiment of the invention, a method of using a power brick with a network adapter includes the following. A high voltage power supply including superpositioned high frequency communications signals is received via a power brick. The voltage of the received signal is reduced.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a stress-follower circuit configuration. The stress-follower circuit of the configuration is coupled to a pad of the integrated circuit. The stress-follower circuit configuration is coupled so as to reduce the voltage stress on the gate of a transistor in a transistor stack so that in operation the transistor in the stack tolerates an operating voltage approximately 1.5 volts above its nominal voltage. The transistor stack is also coupled to the pad.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.

Abstract: Briefly, in accordance with one embodiment of the invention, a DC-to-DC converter package includes: a DC-to-DC converter circuit. The components of the DC-to-DC converter circuit that perform high frequency switching during converter operation are surface mounted on a printed circuit board (PCB) so that the heat produced from the high frequency switching is approximately equally distributed at least over the portion of the PCB where the components are mounted.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes an operational amplifier coupled in a circuit configuration. The circuit configuration includes two transistors coupled to the operational amplifier so that the corresponding voltages at the terminals or ports of the transistors are substantially identical. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes an operational amplifier coupled in a circuit configuration. The circuit configuration includes two circuit components coupled to the operational amplifier so that the corresponding voltages at the terminals or ports of the circuit components are substantially identical. The circuit components include any circuit components capable of implementing a transconductance.

Abstract: Briefly, in accordance with one embodiment of the invention a method of forming at least two vias, each having a metal overlap, to interconnect at least two connection points with metallization includes the following. The at least two vias are etched through a layer of insulating material. The at least two etched vias are located diagonally with respect to one another. Metal overlap for each of the at least two vias is formed into a polygon shape having more than four sides.Briefly, in accordance with another embodiment of the invention, an article includes: a storage medium, the storage medium having stored thereon, instructions, which, when executed, result in: the placement and routing of vias between at least two connection points to be interconnected with metallization by positioning at least two vias diagonally with respect to one another, the at least two vias being positioned so each is capable of having a polygon shape of metal overlap with more than four sides.

Abstract: Briefly, in accordance with one embodiment of the invention, a driver includes: a plurality of transistors and two substantially equal impedances coupled so as to provide a relatively constant source output impedance during switching of a selected subset of transistors of the plurality. The plurality further provides the relatively constant source output impedance at each of two states of the driver output signal. In accordance with anther embodiment, a signaling circuit includes a circuit configuration including the capability to provide high speed, small swing voltage signaling and low speed, rail-to-rail voltage signaling. The circuit configuration is coupled to provide a substantially constant output impedance during high-speed signaling. In accordance with anther embodiment, a method of operating a dual mode circuit providing a substantially constant output impedance in a first operational mode of high speed, limited voltage swing signaling.

Abstract: A DC-to-DC converter includes: a first circuit to sense when the converter output voltage occurs outside a substantially pre-determined range, and a second circuit to adjust the converter load current, based at least in part, upon a signal provided by the first circuit. Alternatively, a circuit to suppress voltage transients for use in a DC-to-DC converter having a primary inductor includes: another circuit inductance lower than the inductance of the primary inductor. The another circuit inductance is coupled in the circuit to be activated when the load voltage of the DC-to-DC converter occurs outside a substantially predetermined range. The another circuit inductance is further coupled in the circuit so that it has the capability to modify the load current during activation.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.

Abstract: Palettized image data for two or more images, represented by color lookup table (CLUT) indices, are mapped to an index space. Blended pixels are generated from the pixels in the index space using alpha blending. The blended pixels are mapped back to CLUT indices to generate palettized blended image data. In a preferred embodiment, in which the CLUT is generated based on a characterized structure in YUV space, the CLUT indices are mapped to Y and UV indices in a YUV index space. The Y and UV indices are then used to generate three-coordinate blended pixels. The three-coordinate blended pixels are then mapped back to CLUT indices of a palettized blended image. Table lookups are used to generate the blended pixels from the Y and UV indices and to map the blended pixels back to CLUT indices.