Patents Represented by Attorney, Agent or Law Firm Howard H. Sheerin
  • Patent number: 6009549
    Abstract: A disk storage system is disclosed wherein user data received from a host system is first encoded according to a first channel code having a high code rate, and then encoded according to an ECC code, such as a Reed-Solomon code, wherein the ECC redundancy symbols are encoded according to a second channel code having low error propagation. In the preferred embodiment, the first channel code is a RLL (d,k) code having a long k constraint which allows for longer block lengths (and higher code rates). During read back, a synchronous read channel samples the analog read signal a synchronously and interpolates the asynchronous sample values to generate sample values substantially synchronized to the baud rate. In contrast to conventional synchronous-sampling timing recovery, interpolated timing recovery can tolerate a longer RLL k constraint because it is less sensitive to noise in the read signal and not affected by process variations in fabrication.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: December 28, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: William G. Bliss, Christopher P. Zook, Richard T. Behrens
  • Patent number: 6005727
    Abstract: A servo decoder is disclosed for disc storage systems that operates according to a novel coding scheme capable of accurately decoding detected codewords representing servo track address during seek operations, even when the recording head flies between two adjacent tracks, and capable of correcting errors in the detected codedwords caused by noise in the read signal, such as inter-symbol interference. In a first embodiment, the coding scheme comprises an error correcting code (ECC) capable of correcting a predetermined number of bit errors in the detected codewords. To achieve the equivalent effect of a conventional Gray code, the codewords are arranged such that adjacent track addresses differ by a number of bits equal to the minimum distance of the ECC code. In a second embodiment, the servo code corrects certain minimum distance error events associated with a trellis type sequence detector.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: December 21, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Richard T. Behrens, Christopher P. Zook, David E. Reed, Stephen A. Turk
  • Patent number: 6005731
    Abstract: A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: December 21, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: William R. Foland, Jr., Richard T. Behrens, Alan J. Armstrong, Neal Glover
  • Patent number: 5999355
    Abstract: A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: December 7, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Richard T. Behrens, William G. Bliss, Li Du, Mark S. Spurbeck, German S. Feyh, Trent O. Dudley
  • Patent number: 5996105
    Abstract: In an optical disk storage device capable of reading compact disks (CDs) and digital video disks (DVDs), the latency of an error correction system is significantly reduced by sharing a syndrome buffer between CD and DVD modes of operation. In CD mode, user data read from the disk is stored in the syndrome buffer and corrected using C1/C2 redundancy of a Cross-Interleaved Reed-Solomon Code (CIRC). In DVD mode, user data read from the disk is stored in a data buffer and the syndrome buffer stores: intermediate values for generating the ECC syndromes for use in correcting the user data, and data CRC and error CRC syndromes for use in verifying the validity and completeness of the corrections. Two aspects of the present invention which significantly increase throughput are (1) the ECC syndromes are generated concurrently for the row (Q) and column (P) codewords of the CD and DVD product codes, and (2) the CRC validation syndrome is generated concurrent with correcting the product code.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: November 30, 1999
    Assignee: Cirrus Logic, Inc.
    Inventor: Christopher P. Zook
  • Patent number: 5991107
    Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, computes a DC offset in the sample values in real time, and subtracts the DC offset from the read signal. This attenuates the deleterious affect a DC offset has on the detection algorithm used to detect the recorded data, such as the Viterbi detection algorithm.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: November 23, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Richard T. Behrens, Trent O. Dudley, Neal Glover, David R. Welland
  • Patent number: 5991911
    Abstract: A compact disk (CD) and digital video disk (DVD) error correction system is disclosed which generates a CRC validation syndrome on-the-fly while correcting the CD/DVD product code, thereby reducing the overall access latency as compared to the prior art. For the DVD product code, which comprises multiple data sectors with separate CRC symbols appended to each data sector, a buffer used for C1 and C2 encoding/decoding in CD mode is used to store partial data and error CRC syndromes for each data sector. During the vertical (P) and horizontal (Q) passes over the DVD product code, data and error CRC syndrome registers are loaded with the appropriate partial CRC syndromes depending on the current data symbol being processed by a P/Q decoder. After processing each data sector, the data and error CRC syndromes for each data sector are combined and compared to a constant to determine whether the corrections to the data sector are valid and complete.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: November 23, 1999
    Assignee: Cirrus Logic, Inc.
    Inventor: Christopher P. Zook
  • Patent number: 5987634
    Abstract: A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: November 16, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Richard T. Behrens, William G. Bliss, William R. Foland, Jr.
  • Patent number: 5978162
    Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. A Channel Quality circuit accumulates various signals generated by the read channel, such as sample errors, gain errors, timing errors, etc., for use in calibrating the read channel components and estimating the bit error rate.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: November 2, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Richard T. Behrens, Kent D. Anderson, Alan J. Armstrong, Trent Dudley, Bill R. Foland, Neal Glover, Larry D. King
  • Patent number: 5974580
    Abstract: An efficient error correction processor is disclosed for correcting a multi-dimensional code comprising a first set of codewords that intersect with a second set of codewords. The error correction is carried out by performing iterative passes over the first and second set of codewords. The individual codewords are corrected using error syndromes which are computed as a function of the codeword data. In the preferred embodiment, the individual codewords are encoded according to a Reed-Solomon code and the error syndromes are computed as the modulo division of the codeword polynomial by the factors of a generator polynomial. To increase the throughput of the error correction processor, a syndrome buffer is employed to facilitate generating the error syndromes for both the first and second set codewords concurrently. In this manner, after a pass over the first set of codewords, the error syndromes for the second set codewords are available for immediate processing.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: October 26, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Christopher P. Zook, Keisuke Kato, Frederick Siu-Huang Au, Tony Jihyun Yoon
  • Patent number: 5966415
    Abstract: A sampled amplitude read channel for disk storage systems is disclosed which asynchronously sub-samples an analog read signal significantly below the Nyquist rate (the baud rate) in order to increase the effective data rate without increasing the frequency of the sampling device. Interpolated timing recovery up-samples the asynchronous samples to generate sample values synchronized to the baud rate, and a Viterbi sequence detector detects the recorded digital data from the synchronous sample values. To compensate for the time-varying characteristics of the recording device, a discrete-time equalizer adaptively equalizes the asynchronous sample values using a least mean square (LMS) adaptive algorithm,W.sub.k+1 =W.sub.k -.mu..multidot.e.sub.k .multidot.X.sub.k,where W.sub.k is a vector of FIR filter coefficients, .mu. is a programmable gain, e.sub.k is a sample error between the FIR filter's actual output and a desired output, and X.sub.k is a vector of samples values from the FIR filter input.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: October 12, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: William G. Bliss, Sian She, David E. Reed
  • Patent number: 5966257
    Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a partial response of the form (1-D)(1+D).sup.n where n>1, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: October 12, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Richard T. Behrens, Alan J. Armstrong, Trent Dudley, Neal Glover, Larry D. King
  • Patent number: 5966258
    Abstract: A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by detecting an estimated binary sequence from a sequence of discrete-time sample values generated by sampling pulses in an analog read signal from a read head positioned over the disk storage medium. The read channel comprises a variable gain amplifier for adjusting the magnitude of the analog read signal before sampling, and a discrete-time gain control loop for generating a gain control signal applied to the VGA in response to the discrete-time sample values. The discrete-time sample values may, or may not be, synchronized to a baud rate of the recorded data. For example, when reading the user data the discrete-time sample values are synchronous, and when reading a servo address mark (SAM) the sample values are asynchronous. As such, the discrete-time gain control loop of the present invention is programmable to operate in a synchronous or asynchronous mode.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: October 12, 1999
    Assignee: Cirrus Logic, Inc.
    Inventor: William G. Bliss
  • Patent number: 5961658
    Abstract: A sampled amplitude read channel is disclosed for disk storage systems that employs an EPR4 remod/demod sequence detector. To reduce the complexity of timing recovery, gain control and adaptive equalization, the channel samples are initially equalized into a PR4 partial response so that a simple slicer circuit can generate estimated sample values. The PR4 equalized channel samples are then passed through a 1+D filter to generate EPR4 equalized channel samples which are processed by an EPR4 Viterbi sequence detector to generate a preliminary binary sequence. The preliminary binary sequence is remodulated into an estimated or ideal PR4 sample sequence which is subtracted from the PR4 equalized channel samples to generate an error sample sequence. An error pattern detector processes the error sample sequence to detect the dominant error events associated with the EPR4 Viterbi sequence detector.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: October 5, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss, Lisa C. Sundell
  • Patent number: 5956304
    Abstract: In an optical disk storage device, a differential phase detector is disclosed for generating a position error signal independent of the frequency content of the recorded data. A pair if diagonal signals S1 and S2 are generated by adding a pair of respective quadrants of a four-quadrant photodetector, where the phase offset between the diagonal signals represents the position error of the pit image as it passes over the photodetector. The position error is determined in the present invention by computing the difference between a positive and negative correlation of the diagonal signals S1 and S2, otherwise referred to as a dual arm correlation (DAC) ##EQU1## where .DELTA. is the correlation offset and L is the correlation length. In the preferred embodiment, the correlation offset .DELTA. is adaptively adjusted to maximize the correlation between S1 and S2. In this manner, the position error estimate is substantially insensitive to the frequency content of the recorded data.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: September 21, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Louis Supino, Paul M. Romano, Larry D. King, German S. Feyh
  • Patent number: 5926490
    Abstract: A sampled amplitude read channel is disclosed for disk storage systems that employs a remod/demod sequence detector guided by an error syndrome of an error detection code (EDC). The remod/demod sequence detector comprises: a conventional trellis type maximum likelihood sequence detector, such as a Viterbi detector, for detecting a preliminary binary sequence from the channel sample values; a syndrome generator for generating an error syndrome in response to the preliminary binary sequence; a remodulator for remodulating the detected binary sequence into a sequence of estimated ideal sample values; a sample error generator for subtracting the channel samples from the estimated samples to generate a sample error sequence; an error pattern detector for detecting potential error events in the sample error sequence; and an error corrector for correcting the preliminary binary sequence when the error syndrome indicates that an error occurred.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: July 20, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss, Lisa C. Sundell
  • Patent number: 5920578
    Abstract: An error detection and correction system is disclosed for efficiently processing a product code typically employed in an optical storage device. In particular, the present invention decreases the processing time associated with iteratively processing the rows and columns of the product code by processing only those code words that were "flagged" during a previous iteration. If, for example, while processing the column code words a byte in a column code word is corrected, then the corresponding intersecting row code word is flagged for processing during the "row pass." Only the row code words that have been flagged are processed during the "row pass", which significantly reduces buffer access latency and increases the overall throughput of the storage system. To assist in error detection and correction, an array of erasure pointers is employed where each erasure pointer corresponds to a byte in a code word.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: July 6, 1999
    Assignee: Cirrus Logic, Inc.
    Inventor: Christopher P. Zook
  • Patent number: 5917668
    Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: June 29, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Richard T. Behrens, Trent Dudley, Neal Glover, David R. Welland
  • Patent number: 5917784
    Abstract: A trellis sequence detector is disclosed for detecting a quadrature servo signal in optical disk storage devices. The quadrature servo signal is generated in discrete time and comprises two sinusoidal signals phase offset by 90 degrees. The sampling frequency of the quadrature signal is controlled relative to the track crossing velocity so as to produce a fixed number of samples per period of the sinusoid (i.e., per track crossing). In the embodiment disclosed herein, the sampling of the sinusoidal signals is controlled such that there are eight samples per track crossing. The eight samples are associated with a state transition diagram and corresponding trellis diagram which define the operation of a trellis sequence detector. The trellis sequence detector processes the actual samples of the quadrature signal to determine an estimated quadrature sequence closest to the actual samples of the quadrature signal.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: June 29, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Louis Supino, Paul M. Romano, Jim Graba
  • Patent number: 5914922
    Abstract: In an optical disk storage device wherein user data is demodulated from a light beam reflecting off data pits in tracks of an optical disk storage medium, a quadrature seek signal is generated indicative of the light beam crossing tracks of the optical disk during a seek operation. The quadrature seek signal is generated from a discrete-time tracking error signal (TES) and a discrete-time RF baseband signal. The discrete-time TES is generated according to the mode of operation, compact disk (CD) or digital video disk (DVD). In CD mode the TES is generated as the difference between E and F tracking photodiodes, and in DVD mode the TES is generated using a discrete-time differential phase detector (DPD). To generate the discrete-time RF baseband signal, the RF data signal (generated as the sum A+B+C+D of a four quadrant photodiode) is sampled at the channel rate and the RF data samples passed through a discrete-time envelope detector.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: June 22, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Louis Supino, Jim Graba, Shuangxia Zhu, Paul M. Romano