Abstract: A disk drive is disclosed comprising a disk, a spindle motor for rotating the disk, an actuator arm, and a head coupled to the actuator arm. While powered down the head is latched in a parked position. During a start-up process, the spindle motor is controlled to rotate the disk toward an operating speed and the head is unlatched prior to the disk reaching the operating speed. If the disk drive is in a first spin-up mode (e.g., a normal spin-up mode) the head is unlatched relative to a first target speed, and if the disk drive is in a second spin-up mode (e.g., a re-sync spin-up mode) the head is unlatched relative to a second target speed greater than the first target speed.

Abstract: A disk drive is disclosed comprising a disk, a head, an actuator arm for actuating the head radially over the disk during a seek operation, and a voice coil motor (VCM) for rotating the actuator arm about a pivot, the VCM comprising a coil comprising a VCM resistance R. A back EMF voltage detector measures a back EMF voltage across the coil, and a current detector detects a current I flowing through the coil. An IR voltage detector, responsive to the current I detected by the current detector, detects an IR voltage proportional to the current I times the VCM resistance R. A voltage compensator substantially cancels the IR voltage from the measured back EMF voltage to generate a compensated back EMF voltage. A control voltage generator, responsive the compensated back EMF voltage, generates a control voltage applied to the coil to generate the current I flowing through the coil. A memory stores a first compensated back EMF voltage generated at a first time period of the seek operation.

Abstract: A disk drive comprising a programmable inverting voltage regulator (PIVR) for generating an inverted voltage supply applied to a preamp is disclosed. The PIVR is programmably configured relative to the disk drive's mode of operation, including a read mode and a write mode.

Abstract: A disk drive is disclosed comprising a head, a spindle motor having a hub, the hub comprising a cylindrical shaft, the shaft defining a generally cylindrically-shaped outer surface, the outer surface defining a latching member extending around at least part of the circumference of the shaft. A disk is positioned on the spindle motor and an actuator moves the head radially over the disk. A disk clamp clamps the disk to the spindle motor. The disk clamp comprises a ring-shaped body comprising an outer ring-shaped surface abutting the disk, and an inner neck spaced-apart from the outer ring-shaped surface, the inner neck comprising a plurality of independently flexing teeth for contacting the latching member.

Abstract: A disk drive is disclosed comprising a disk, a spindle motor for rotating the disk, and a head actuated radially over the disk. A disk clamp clamps the disk to a hub of the spindle motor, wherein the disk clamp comprises a notch at a predetermined location along an outer diameter of the disk clamp. The disk is aligned non-concentric with the hub such that a center of the disk is aligned offset from a center of the hub toward the notch. The notch substantially counteracts an imbalance due to the non-concentric alignment of the disk with respect to the hub.

Abstract: A disk drive is disclosed comprising a voice coil motor (VCM) actuator and a piezoelectric (PZT) actuator. The VCM actuator is driven by a control effort including an integrator, and the PZT actuator is driven by a control effort including a transformer.

Abstract: A disk drive is disclosed comprising a disk and a semiconductor memory comprising addressable locations for staging and caching data, wherein each addressable location having an allocation status. When a large write command is received from a host to write write-data to the disk, a disk controller dynamically allocates a plurality of the addressable locations relative to the size of the write command and the allocation status of the addressable locations. The write-data received from the host is stored in the dynamically allocated addressable locations while concurrently reading the write-data from the dynamically allocated addressable locations and writing the write-data to the disk. The dynamically allocated addressable locations are re-used for storing write-data received from the host after writing the write-data to the disk.

Abstract: A switched node for use in a multi-dimensional switched fabric network is disclosed. The switched node comprises adapter circuitry connected to receive asynchronous and isochronous packets from an external entity. Each asynchronous packet comprises destination node routing information and data, and each isochronous packet comprises a path ID corresponding to a reserved path through the network, an arrival time parameter identifying a target arrival time of the isochronous packet into the switched node, and data. An asynchronous-to-isochronous converter converts the asynchronous packets into isochronous packets comprising the data from the asynchronous packets.

Abstract: A disk drive comprising a disk for storing encrypted data is disclosed. The disk drive comprises a first circuit for providing plaintext data to a second circuit. The second circuit comprises controllable encryption circuitry for encrypting the plaintext data into the encrypted data. The controllable encryption circuitry comprises a data input, an enable input, and a data output. The second circuit further comprises a plaintext input for providing the plaintext data to the data input, an encrypted text output for providing the encrypted data from the data output, and a first control input for receiving a first device authentication signal for authenticating the first circuit. The second circuit comprises a first verification circuit, responsive to the first device authentication signal, for producing a first verification signal for use in controlling the enable input of the encryption circuitry to enable the encryption circuitry to provide the encrypted data via the encrypted text output.

Abstract: A method and apparatus is disclosed for converting raster images into a vector format by identifying and converting the borders of image features into a mathematical format referred to as string sequences. To enable the string sequencing of color images, the present invention identifies and resolves contrast conflicts in the image features in order to avoid misperceiving the vectorized image when converted back into a raster format. A contrast conflict occurs when there is a “contrast tie” between overlapping features of the image. The feature that would normally be perceived as the dominant feature breaks the contrast tie so that when the vector image is reconstructed, the dominate feature appears in the foreground of the image while the recessive feature appears in the background.

Abstract: A disk drive is disclosed comprising a disk having a plurality of tracks, each track comprising a plurality of blocks. A semiconductor memory comprises a cache buffer having a plurality of segment pools, each segment pool comprising a plurality of cache segments, each cache segment comprises at least one block, and the number of blocks in each cache segment varies between segment pools. When a host command is received, the command size is compared to a threshold in order to allocate a cache segment from a first segment pool or a second segment pool.

Abstract: A disk drive comprises a disk, an actuator arm, a head attached to the actuator arm, a voice coil motor, a parking latch for latching the actuator arm in a latched position in order to park the head during a non-operating mode, a post, and an inertial latch for maintaining the actuator arm in the latched position when the disk drive is subjected to a physical shock. The inertial latch comprises a body having a protruding arm and a pivot surface, wherein during the physical shock the body rotates about the pivot surface such that the protruding arm engages the actuator arm. The body of the inertial latch further comprises a strip-spring comprising a first end inserted into a first receptor and a second end inserted into a second receptor such that the strip spring has an initial arc displacement when installed into the body of the inertial latch.

Abstract: A phase locked loop (PLL) circuit is disclosed comprising a phase detector for generating a phase error between an input oscillating signal and an output oscillating signal. A fractional frequency synthesizer (FFS) generates the output oscillating signal in response to the phase error, wherein the FFS comprises an input for receiving a reference oscillating signal, and a fractional divider responsive to variables I and Fr. The variable I is an integer value, and the variable Fr is a fractional value, both of which are generated in response to the phase error.

Abstract: A disk drive is disclosed comprising a head disk assembly (HDA) including an enclosure for housing a disk and a head actuated radially over the disk. A printed circuit board assembly (PCBA) is attached to the HDA enclosure, wherein the PCBA comprises at least one attached electrical component. A non-electrically conductive coating is bonded to at least part of the PCBA after attaching the electrical component to the PCBA.

Abstract: A switched node is disclosed for use in a switched fabric network. The switched node comprises a disk and a head actuated over the disk. An integrated disk controller within the switched node comprises more than two bi-directional ports for simultaneously transmitting data in multiple directions through the switched fabric network, each port comprising an input port and an output port. The disk controller circuitry further comprises interface circuitry for interfacing with the head, a data buffer for storing data received from the input ports and data received from the head via the interface circuitry, and routing circuitry responsive to header data received from the input ports and header data received from the interface circuitry.

Abstract: A preamplifier circuit is disclosed comprising a data input for receiving write data, a read signal output for outputting an amplified read signal, a read signal input for receiving a read signal from a read element, and a write signal output for supplying a write signal to a write element. The preamplifier circuit further comprises a first amplifier circuit, responsive to the write data, for generating the write signal supplied to the write element, and a second amplifier circuit for amplifying the read signal from the read element to generate the amplified read signal output via the read signal output. A head control circuit, responsive to head select data, simultaneously enables the first and second amplifier circuits to perform a simultaneous read and write operation.

Abstract: A communication channel is disclosed comprising a trellis sequence detector for detecting an estimated data sequence from signal sample values. A post processor detects and corrects an error event of the trellis sequence detector by remodulating the estimated data sequence into a sequence of expected sample values, computing samples errors as the difference between the expected samples and signal samples, and correlating the sample errors with error event samples. The communication channel further comprises a Reed-Solomon error correction code (ECC) decoder for decoding a Reed-Solomon codeword in the estimated data sequence in response to the detected error event.

Abstract: A network switch is disclosed for resolving requests from a plurality of host initiators by scheduling access to a plurality of storage systems. The network switch comprises a plurality of multi-port switches interconnected to form a switched fabric, the multi-port switches for routing requests to the plurality of storage systems and for receiving scheduling data from each of the plurality of storage systems. The network switch further comprises a memory for storing the scheduling data, and a microprocessor, responsive to the scheduling data stored in the memory, for executing a scheduling algorithm to schedule the requests. The scheduling data is transferred automatically from each storage system to the memory through the multi-port switches without the microprocessor requesting the scheduling data from each storage system.

Abstract: A disk drive is disclosed comprising a disk, a head, an actuator arm for actuating the head radially over the disk, a fixed object, and a voice coil motor (VCM) for rotating the actuator arm about a pivot, the VCM comprising a coil comprising a VCM resistance R. A back EMF voltage detector measures a back EMF voltage across the coil, and a current detector detects a current I flowing through the coil. An IR voltage detector, responsive to the current I detected by the current detector, detects an IR voltage proportional to the current I times the VCM resistance R. A voltage compensator substantially cancels the IR voltage from the measured back EMF voltage to generate a compensated back EMF voltage. A control voltage generator, responsive the compensated back EMF voltage, generates a control voltage applied to the coil to generate the current I flowing through the coil.

Abstract: A disk drive is disclosed comprising a disk, a head, and an actuator for actuating the head radially over the disk. The disk comprises a plurality of tracks, wherein each track comprises a plurality of sectors. The plurality of sectors comprise a plurality of data sectors for storing data and at least one sector-reconstruction (SR) sector for storing redundancy data generated in response to the data stored in at least one of the data sectors. At least two of the plurality of sectors of a track are for storing a SR status indicating a validity of the SR sector stored on the track.