Abstract: An apparatus, device, or inlet port plug, may close an inlet port that is formed in a sheet of flexible material. The inlet port is adapted for mounting on an inflatable device and is shaped and constructed to receive and retain an air hose nozzle through which air flows to inflate the inflatable device. The inlet port plug blocks the inlet port when no air hose nozzle is engaged. Consequently, air cannot easily pass out of the inflatable device through the inlet port when the device is inflated or being inflated. The inlet port plug has a generally planar shape with coplanar extensions extending radially from a plug body. The inlet port plug may be engaged with an inlet port by causing at least two of the extensions to be received in the inlet port. When the extensions are received, the plug is retained against the inlet port.

Abstract: An integrated circuit according to the present invention includes application-specific circuitry and an embedded counter assembly capable of measuring the frequency of one or more clock signals, which may be generated internally by the integrated circuit or externally by one or more sources external to the integrated circuit. The embedded counter assembly utilizes a reference clock signal having known characteristics, and measures the frequency of an unknown clock signal based upon the reference clock signal. The embedded counter assembly is capable of measuring the frequency of internal clock signals that are otherwise inaccessible via external output pins.

Abstract: An impedance element connecting the outputs of two transistors of a wide-bandwidth amplifier forms a zero. The output of transistor is connected to a current source. The wide-bandwidth amplifier has a bandwidth greater than conventional amplifiers utilizing a single current source without an increase in power dissipation.

Abstract: A low-jitter phase-locked loop (PLL) circuit includes a reference signal generator and a PLL. The reference signal generator is configured to quadruple a frequency of a first reference signal to produce a second reference signal. The PLL includes a filter coupled in series with a voltage controlled oscillator (VCO), and a frequency phase detector configured to generate a first error signal based on a frequency difference between the second reference signal and a first divided VCO output signal. The PLL further includes a phase detector configured to generate a second error signal based on a phase difference between the second reference signal and a second divided VCO output signal at each rising and falling transition of the second reference signal.

Abstract: A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.

Abstract: A high speed phase detector utilizes an integrated XOR/SUMMER/MUX circuit having a higher bandwidth and lower power than conventional designs. The XOR/SUMMER/MUX circuit combines the functionality of two parallel XOR devices in series with a summer/multiplexer in a manner that reduces the number of gate delays associated with the input signals. In a practical implementation, the XOR/SUMMER/MUX circuit includes XOR arrangements having a plurality of transistors implemented at a first transistor level and a plurality of transistors implemented at a second transistor level. The XOR/SUMMER/MUX circuit also includes transistors implemented at a third transistor level; these transistors are utilized by the multiplexer feature of the circuit.

Abstract: A tissue treatment apparatus is provided which includes a thermally conductive bandage, a heater in thermal contact with the bandage over a tissue treatment area, a heat spreading means acting between the heater and the bandage for laterally spreading heat transferred from the heater to the bandage in order that heat be substantially uniformly distributed across the bandage.

Abstract: A flip-chip transition interface structure is suitable for use in high speed applications that require low return losses. The transition interface includes a conductive signal element and two conductive reference elements formed on a flip-chip die substrate. A signal solder bump is located at a signal bond pad formed at an end of the conductive signal element, and a reference solder bump is located at each conductive reference element. The conductive elements are configured to form a substantially round cutout region surrounding the signal bond pad. The positions of the solder bumps on the respective conductive elements are selected in a manner that enhances the impedance matching of the transition interface structure.

Abstract: A system and method have been provided for determining a frequency tolerance between a generated clock and an input data rate. The invention analyzes beatnotes, externally generated through a comparison of clock and input data rates, and an overflow count of the clock. The occurrence of overflow counts, without intervening beatnotes, indicates that the clock and data rate are close in frequency. The occurrence of beatnotes without intervening overflow counts indicates that the clock and data rates are not close in frequency. Hysteresis is built into the system, preventing the system from indicating an out-of-lock condition when the beatnotes immediate follow the an overflow count, or when the system monitors occasional beatnotes.

Abstract: A programmable phase locked-loop (PLL) active filter circuit is provided which includes networks of cooperating bandwidth tuning components to select bandwidth ranges. The values and arrangement of the network of selectable series input (R1) resistors are chosen to be useful in both low band and high band settings. Likewise, the opamp network of feedback resistors (R2) and capacitors (C1) values are chosen to be useful in both low band and high band applications, automatically pairing with the R1 selection in response to a bandwidth range selection. These tuning components, internal to an integrated circuit, can be used for a plurality of wideband loops. External components can be used to supplement the internal components for low and high bandwidth applications.

Abstract: An elastic store circuit using a first in/first out buffer (FIFO) to accurately delay and manipulate a waveform using the write (WR) and read (RD) clocks is provided. The FIFO delays data by, first, reading the input data at the WR clock rate. Then, the data exits the FIFO in response to the RD clock. Large delays are accomplished by changing the relationship between the WR and RD clocks in whole clock intervals. Delays and adjustments of less than a whole clock interval are accomplished by changing the phase relationship of the RD clock with respect to the WR clock. The present invention generates the WR and RD clocks through synthesis using a lower frequency reference clock. The RD phase change results from introducing a phase change into the reference clock driving the RD clock synthesizer. A method of introducing precise delays through phase control of the WR and RD clocks is also provided.

Abstract: An electronic device package includes a multilayer substrate having an interconnect structure configured to propagate a high frequency signal from one metal layer to another metal layer. The configuration and layout of the interconnect structure, particularly the arrangement of the reference vias associated with the signal via, is selected such that a desired filter response is achieved. The filter response is realized without any additional capacitor or inductor components. Thus, the natural discontinuity created by the vias and the inherent parasitic capacitance and inductance associated with the vias can be utilized to create a desired lowpass or bandpass filter response.