Abstract: Cooling pads, mattresses, and limb-conforming sleeves reduce a person's temperature by evaporative and/or conductive cooling. An open cell foam pad defines an internal air flow passages proceeding according to serpentine or other desired routing. The pad is wetted, and a blower circulates air through the air flow passage and evaporatively cools the pad by removing warm water vapor. By contacting the cooled structure, the person is conductively cooled. The pad also employs evaporative cooling if water is permitted to seep from the foam pad onto the person's skin and subsequently evaporate. Another cooling device is a multi-layer evaporative cooling mattress. The mattress comprises an open cell foam structure having a person-receiving side and a base side. At the person-receiving side lies an absorbent layer with internal liquid delivery lines, and optionally having an outer film applied thereto.

Abstract: An electronic package component includes a flip-chip device mounted to a BGA substrate. The BGA substrate includes conductive traces formed on its upper surface and configured in a coplanar waveguide structure. The package includes a dielectric coating applied over the conductive traces and over the upper surface of the substrate. The coating is formed from a material having a dielectric constant that is equal to or approximately equal to the dielectric constant of the BGA substrate material. The dielectric coating reduces the adverse effects caused by phase velocity dispersion of the signal propagated by the coplanar waveguide.

Abstract: A circuit and method for de-skewing a global clock tree is disclosed. A circuit uses a digital delay lock loop having an incoming clock input, a local reference clock input, and a clock output providing an output clock signal. The delay lock loop receives an incoming clock signal and aligns it with a local reference clock signal, where the incoming clock signal is a skewed version of the local reference clock signal. The circuit further includes a clock tree for receiving the output clock signal and outputting a global clock signal when the delay lock loop is in lock mode. The output clock signal of the global clock tree represents a phase lock between an incoming clock signal on the incoming clock input and a local reference clock signal input on the local reference clock input.

Abstract: A method of reducing jitter in a phase locked loop (PLL) includes receiving a first reference signal, quadrupling a frequency of the first reference signal to produce a second reference signal, and providing the second reference signal to a frequency phase detector of the PLL. The method may also include equalizing the second reference signal prior to providing the second reference signal to the frequency phase detector. The method can be accomplished by a circuit, wherein quadrupling the frequency of the first reference signal is performed by two frequency doublers arranged in series. The step of equalizing can be performed by two equalizers, each one configured to equalize an output of a respective frequency doubler.

Abstract: An integrated device having a transimpedance amplifier (TIA) cascaded with a limiter can be tested such that the frequency response of the TIA is accurately measured. The frequency response of the TIA is derived from the measured output jitter response of the integrated TIA/limiter device. In a practical testing system, a sinusoidal test signal having a constant amplitude is combined with a broadband noise signal having a constant power level to obtain a noisy test signal. The TIA/limiter is driven by the noisy test signal while the frequency of the test signal is varied. The output jitter of the TIA/limiter is measured for a number of frequency settings to obtain the output jitter response.

Abstract: A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.

Abstract: Circuitry for a phase locked loop (PLL) includes a reference signal input and a frequency doubler. The output of the frequency doubler is a second reference signal having a frequency that is approximately twice that of the initial reference signal, and which is fed into the PLL. The frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The frequency doubler can include one or more additional delay circuits in series after the first delay circuit, the output of which is provided to a multiplexer. The multiplexer includes a selection signal input for selecting an output from at least one of the delay circuits to be provided to the XOR circuit. The frequency doubler allows the PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter.

Abstract: Cooling devices are provided to reduce a person's temperature by evaporative, convective, and/or conductive cooling. One such device maximizes evaporative cooling by aiding the flow of air to the person and the removal of vapor-laden air from the person. An upper sheet and a base sheet are adhered to define numerous elongated, parallel, inflatable cooling chambers separated by flat connecting membranes. Ventilating cross-members interconnect the cooling chambers. Air enters the chambers through an inlet, exits the chambers toward the person through air permeable regions of the base sheet. Air heated by the person's body exits the device upward through evaporation openings in the connecting membranes. The foregoing device, or different variations thereof, may be modified for use in conductive cooling by adding an absorbent sheet beneath the base sheet, or substituting the absorbent sheet for the base sheet itself.

Abstract: An amplitude of a differential output signal at a differential multiplexer is maximized by presenting, in response to a differential selection signal, a high impedance to each output port of each differential transistor of a non-selected differential transistor pair. A differential input signal is received at each differential transistor pair. Each transistor of each differential transistor pair is connected to a current source through an independent selection transistor. In response to the differential selection signal, each of the selection transistors is placed in an off state resulting in a high impedance between the output ports of the transistors of the non-selected differential transistor pair.

Abstract: A wound treatment apparatus is provided which includes a bandage that is transparent to, or transmissive of, energy in the infrared (IR) range of the electromagnetic spectrum, a heater that generates heat, and an attachment device for retaining the heater over or on the bandage. The bandage and heater together have a low profile so as to be convenient for a patient, and are flexible so as to conform to the shape of a wound and to contours of the skin near the wound. The bandage is provided with an adhesive pattern for maintaining moisture at the wound site. The heater may maintain a normothermic condition at the wound treatment area. A controller may be provided for cycling the temperature of the heater in order to maintain the normothermic condition.

Abstract: A system and method are provided for using an analysis of forward error corrections (FEC) in a digital communications signal as feedback information to improve the performance of an analog receiver system. The FEC decoder supplies the number of “1” bit and “0” bit corrections made to a control unit. In response to the FEC corrections, the control unit changes receiver control parameters. The control signal modifies processing in the receiver front end to achieve the fewest number of FEC corrections.

Abstract: An electronic package, such as a ball grid array (“BGA”) package, includes a high speed signal trace formed at a conductive layer and a corresponding reference plane formed at another conductive layer. The reference plane includes a cutout region formed therein; the cutout region is positioned over the signal solder ball to which the high speed signal trace is coupled. The lateral center point of the cutout region is offset relative to the lateral center point of the signal solder ball. The offset configuration reduces the capacitance between the signal solder ball and the reference plane and improves the high frequency transmission characteristics of the electronic package.

Abstract: An iterative method involves performing a coarse frequency correction process which adjusts receiver frequency so that a pilot tone signal is within a predetermined frequency range and, after performing the coarse frequency correction process, performing a fine frequency correction process which adjusts receiver frequency so that the pilot tone signal is substantially aligned with a pilot tone reference within the predetermined frequency range. By performing these processes, the receiver frequency may be adjusted so that the alias pilot tone signal is substantially aligned with the pilot tone reference and the pilot tone signal is undesirably shifted outside the predetermined frequency range. To eliminate this condition, the method further involves performing the coarse frequency correction process again and, after performing the coarse frequency correction process again, performing the fine frequency correction process again.

Abstract: A CMOS field effect transistor (FET) is provided with predetermined temperature characteristics. More particularly, the relationship between the channel length, gate width, gate-to-source voltage, and drain current is exploited to create an FET that has relatively constant drain current across a relatively wide range of frequencies. Alternately, the above-mentioned relationship is exploited to create a drain current with a predetermined temperature coefficient across a wide temperature range.

Abstract: A system and method is provided for in situ testing of communications links employing digitally wrapped communications. Portions of the payload to be wrapped are replaced with test patterns. These test patterns can be sent simultaneously with real information. The invention provides that the receiving node generate a test pattern, extract the transmitted test pattern, and determine errors in response to comparing the two test patterns. Analysis of the errors can be used to determine the state of the link between the transmitting and receiving nodes.

Abstract: A ring oscillator integrated circuit is provided that is comprised of a plurality of parallely arranged ring oscillator sections, where a ring oscillator section can be any conventional ring oscillator circuit. That is, the inputs and the outputs of a plurality of conventional ring oscillators are connected together. Since each ring oscillator section output signal includes random noise, the parallel arrangement of ring oscillators, and the summing of several oscillator signals, causes at least some noise cancellation. As a result, a lower noise oscillator signal is supplied. A method of reducing random noise in a ring oscillator circuit is also provided.

Abstract: A dual loop system for the acquisition and tracking of a carrier signal is presented. The acquisition loop uses a bang-bang phase detector which permits the carrier to be acquired without a clock reference. Once acquired, the carrier is then tracked with a loop using a Hogge phase detector. The tracking loop is autoscaling, so that loop gain and bandwidth are responsive to the carrier signal frequency. The autoscaling feature of the tracking loop and the uniform gain of the acquisition loop permit the same loop filter to be shared by both loops. A method implementing the above-described dual-loop system is also presented.

Abstract: A biasing circuit for producing a bias current which is supply-independent and temperature-stable includes a first voltage generating circuit which produces a first voltage V1 at an output; a second voltage generating circuit which produces a second voltage V2 different from the first voltage V1 at an output; a differential amplifier circuit having inputs coupled to the outputs of the first and the second voltage generating circuits and producing a reference voltage VREF based on a difference between the first voltage V1 and the second voltage V2; and a current generating circuit which produces a bias current IREF from the reference voltage VREF.

Abstract: In a convective treatment system a wind-actuated instrument mounted near an end of an air hose provides, generates, issues, or sounds an audible alarm when the end becomes disconnected from a convective device and pressurized air continues to flow through the end. The instrument may be mounted on an interface device receivable on the end. The interface device may include means for reducing or stopping the flow of air through the end in response to the disconnection.

Abstract: An elastic store circuit using a first in/first out buffer (FIFO) to accurately control the phase delay in a waveform using the write (WR) and read (RD) clocks is provided. The FIFO reads the input data at the WR clock rate. The data exits the FIFO in response to the RD clock. Large delays are accomplished by changing the relationship between the WR and RD clocks in whole clock intervals. Delays and adjustments of less than a whole clock interval are accomplished by changing the phase relationship of the RD clock with respect to the WR clock. The present invention generates the WR and RD clocks through synthesis using a lower frequency reference clock. The RD clock phase change results from phase-locking the RD clock to a phase offset version of the reference clock. A method of introducing precise delays through phase delay of the RD clock with respect to the reference clock is also provided.