Abstract: A lateral bipolar transistor and method of making the transistor which is compatible with a method of making MOS transistors to be used in making BICMOS circuits are disclosed. The method includes the following steps: Forming on the surface of a substrate of one conductivity type at least one layer of a semiconductor material of the opposite conductivity type. Forming a first region of the opposite conductivity type into one portion of the layer in one of the portions of the layer and a highly conductive contact region to the layer in another portion, forming a layer of an insulating material over the layer and providing an aperture therethrough to the first region. Depositing a layer of polycrystalline silicon over the insulating layer and in the aperture and defining the polycrystalline silicon layer so that it is in the aperture and extends a short distance beyond the aperture but not beyond the edge of the first region.

Abstract: An orthopedic pacifier, which is useful to inhibit or correct a receding lower jaw condition for improved placement of the upper and lower alveolar ridges of an infant's mouth, includes a shield to border the lips, a resiliently deformable bulbous body and a bridge connecting the base end of the body to the shield. The bridge extends between the upper and lower alveolar ridges from the base end to the shield and positions the body with its free end located posteriorly in the mouth. The body has a palatal conforming upper portion, and a lower portion defining an inclined section extending from the base end to the free end to engage the posterior side of the lower alveolar ridge to guide the lower jaw forward to foster its potential to grow into normal position relative to the upper jaw. A depression in the free end guides tongue placement to direct its forces toward the palate to improve control for swallowing.

Abstract: A baseball board game comprising a board having a baseball field depicted thereon. The field is divided into nine square areas each designated by a single digit number. Each of the square areas is divided into thirty six small squares each designated by a two digit number. Several different types of pitches are listed on the board and each has thereunder a group of two digit numbers. Several groups of hitting two digit hitting numbers are listed on the board, and a group of field two digit numbers are arranged in a plurality of rows on the board. Each row of the field numbers is headed by a different single digit number corresponding to the number of large square areas on the board. The digits of each of the two digit numbers is from "1" to "6", and the second digit of each of the numbers is of a color different from that of the first digit. A plurality of markers are provided to indicate the members of each of the teams and a separate marker is used to indicate the ball.

Abstract: A word game assembly for play by two or more players includes for each player a play grid of horizontal and vertical rows of adjacent areas and a supply of alphabetical letter designating play pieces receivable on the grid areas in a competitive attempt to form words. A player operated random selector and indicator device, such as a spinnable top having side facets marked with different symbols, is used to determine the nature and procedure of play for effecting a series of plays. For instance, each player may select play pieces and place them on an associated play grid to form words in dependence upon the indicated random selection resulting from a spin of the top. In one embodiment of the word game assembly, a portion of the play grid is rotatable.

Abstract: A microposition table is held in place by the friction between a series of plates contacting one another. Movement is effected by forcing a small burst of air through a series of channels to drive metal pistons each held captive inside an elongated cylinder. The impact of each piston striking one or the other of the cylinder ends imparts sharp mechanical impulses to each plate driving the plate a small distance in the direction of the impacting force. Repeated impacts by repeated bursts of air move the plates the desired distances with respect to one another.

Abstract: A device for measuring the performance of high speed integrated circuits (ICs) while in wafer form consists of one or more miniature coaxial transmission lines for carrying the test signals to and from test instruments. Each of the miniature coaxial cables has a standard connector at one end for connection to testing instruments. The other end of each cable has its center conductor extended beyond the shield of the cable and formed into a conical point for connection to test pads on the IC. One or more miniature leaf springs are attached to the shield. The leaf springs are adapted so that during a probing operation they contact the test pads first and thereafter flex to allow the center conductors to make contact to other test pads. The miniature coaxial transmission lines also flex to limit forces which could otherwise damage center conductors or the test pads.

Abstract: An Electrically Erasable Programmable Logic Array (EEPLAS) (10,000) has an AND plasma (10,002) having a first array (10) of devices (Md11 through MDMN) each containing nonvolatile upper and lower memory cells that each have two serially connected field effect transistors (STUC, MTUC and STLC,MTLC), and an OR plane (10,004) having a second array (12,600) of memory cells with each cell being the same as the cells of the first array (10), and output inverting buffers (12,400). Bit lines (BLa1 through BLaN) of the first array (10) are coupled to word lines (WL1a through WLNa) of the second array (12,600). Each bit line (BLf1 through BLfx) of the second array (12,600) is connected to an input terminal of an inverting buffer (12,400). The outputs of the inverting buffers (12,400) serve as the Electrically Erasable Programmable Logic Array (10,000) output terminals. Each of the memory cells is an electrically erasable nonvolatile cell.

Abstract: A sense amplifier latch voltage waveform generator circuit provides an output voltage waveform which first increases to a first potential level, which is just below the threshold voltage of a field effect transistor, and subsequently increases with an ever-increasing slope over a useful voltage range. The generated voltage waveform is applied to the gate terminal of a latch field effect transistor, which is part of a sense amplifier circuit that includes a cross-coupled pair of field effect transistors whose sources are coupled to the drain of the latch transistor and whose drain terminals receive differential memory signals. The generator circuit consists essentially of an input gating transistor, an output stage having serially connected pull-up and pull-down transistors, and another similar feedback stage which includes a bootstrap capacitor. The bootstrap capacitor is coupled to the output stage.

Abstract: A gated diode switch (GDS1, GDS3, GDS4, GDS10) requires a voltage applied to the gate which is more positive than that of the anode and cathode in order to break current flow between the anode and cathode. In addition, a current of at least the same order of magnitude as flows between anode and cathode must flow into the gate of the switch to break current flow. The use of a second gated diode switch (GDS2, GDS20) coupled by the cathode (28, 280) to the gate of a gated diode switch (GDS1, GDS3, GDS4, GDS10) which is to be controlled provides a high voltage and current capability means for cutting off (interrupting) or inhibiting current flow through the gated diode switch (GDS1, GDS3, GDS4, GDS10). The state of a gated diode switch (GDS1, GDS3, GDS4, GDS10) is thus controlled by a second gated diode switch (GDS2, GDS20).

Abstract: A multibit counter circuit uses a plurality of essentially identical stages which each have a feedback circuit, a flip-flop, and a carry circuit. Each of the stages is connected together in essentially the same way. A counter circuit of any desired bit capacity can be relatively quickly and easily formed with a saving in silicon area compared to standard configurations.

Abstract: The conductivity of a wide range of carbon-containing materials is substantially increased by irradiation with particles having an atomic mass of at least 1. Both polymeric and nonpolymeric, organic and inorganic, materials can be used. The particulate irradiation, for example an ion beam, substantially breaks down the material to a form that includes amorphous carbon having unusually high conductivity. Resistivities of less than 10.sup.-3 ohm-cm are possible. When applied as a film on a substrate, the irradiated material can be used for device interconnects. Conducting lines can be produced in the film, as well as vertical contacts through the film.

Abstract: Set-Reset Master-Slave Flip-Flop circuitry uses a feedback circuit connected to a circuitry output terminal and to set and reset input terminals to limit the effect of spurious signals such that only signals applied to set and reset terminals which are of the appropriate state at least prior to and during the transition of a clock signal from the low to the high state cause the output terminals of the Flip-Flop to be set to or maintained in preselected levels.

Abstract: A folded bit line configured DRAM, with standard even and odd rows of memory cells, also includes spare even and odd rows of memory cells which can be substituted for standard rows found to have defective cells or interconnections. Each of the decoders associated with a standard row includes provision for being disconnected if found to be associated with a defective row. One common spare decoder is associated with one spare even and one spare odd row of memory cells. Each spare decoder is designed normally to be deselected for any address but to be able to assume the address of any disconnected standard row. Disconnection of a standard decoder and substitution of a spare decoder with the appropriate even or odd row are made possible by appropriate inclusion of fusible links which are selectively opened by laser irradiation. The use of one spare decoder with both an even and odd row serves to reduce the number of needed spare decoders and thus reduces overall chip size.

Abstract: A semiconductor structure contains two interconnected gated diode switches in a common dielectrically isolated semiconductor tub. This structure functions as a bidirectional switch. A gate region physically located between the two switches provides electrical isolation to allow proper operation.

Abstract: Control circuitry used with the combination of a control switch (typically a gated diode switch GDS) which is coupled to a control (gate) terminal of a like load switch which consists essentially of first and second p-n-p transistors. The collector of the first p-n-p transistor is coupled to an anode of the control switch. The emitter of the first p-n-p transistor is coupled to the base of the second p-n-p transistor and to a control circuitry input terminal. The collector of the second p-n-p transistor is coupled to a gate terminal of the control switch. The control circuitry limits undesirable current flow into the load switch and has fewer components than commonly used control circuitry which performs a like function.

Abstract: The combination of an amplifier with a capacitor connected between an input and output terminal is coupled to a data bus to effectively reduce the effective capacitance on the bus and thus enhance the response time of information sent through the data bus.

Abstract: Bidirectional circuitry, which includes two amplifiers, each having a capacitor connected between an input and an output terminal thereof, and two interrupt transistors, acts to provide amplification and/or level shifting of information between two transceivers while also reducing capacitive loading and thus enhancing response time.

Abstract: Solid-state shift register circuits, which have right and left shift capability and asynchronous set and clear, and asynchronous and synchronous parallel load capability are formed using a modified form of emitter function logic. These multicontrol shift register circuits achieve relatively high speed operation and have relatively low power dissipation, while requiring only a modest amount of silicon for implementation.

Abstract: A delay gate circuit consists of first and second stages which each have two serially connected MOS transistors and of a fifth MOS transistor. The gates of the transistors of the first stage serve as first and second circuit input terminals. The gate of the second transistor of the first stage is connected to the gate of the first transistor of the second stage. An output terminal of the first stage is connected to the gate of the second transistor of the second stage and to the drain of the fifth MOS transistor. An output terminal of the second stage is connected to the gate of the fifth transistor and serves as the output circuit terminal.

Abstract: To switch a first gated diode switch (GDS1) to the "OFF" state requires a voltage applied to the gate which is more positive than that of the anode or cathode and a sourcing of current into the gate of substantially the same order of magnitude as flows between the anode and cathode of the first switch. Control circuitry, which uses a second gated diode switch (GDSC) coupled by the cathode to the gate of the first switch (GDS1), is used to control the state of the first switch (GDS1). The control circuitry comprises a first branch circuit coupled to the gate of GDSC and to a first potential source +V1 and a second branch circuit coupled to the anode of GDSC and to a second potential source V2. The first branch circuit is connected to the gate of the second switch (GDSC) and controls the state thereof. The second branch circuit helps switch the first switch to the OFF state by providing a single current pulse or a plurality of current pulses into the gate of the first switch.