Abstract: To switch a first gated diode switch (GDS1) to the "OFF" state requires a voltage applied to the gate which is more positive than that of the anode or cathode and a sourcing of current into the gate of substantially the same order of magnitude as flows between the anode and cathode of the first switch. Control circuitry, which uses a second gated diode switch (GDSC) coupled by the cathode to the gate of the first switch (GDS1), is used to control the state of the first switch (GDS1). The control circuitry comprises a first branch circuit coupled to the gate of GDSC and to a first potential source +V1, a second branch circuit coupled to the anode of GDSC and to a second potential source +V2, and a third branch circuit coupled to the anode of GDSC and to a third potential source +V3. The first branch circuit is connected to the gate of the second switch (GDSC) and controls the state thereof.

Abstract: A solid-state protector circuit utilizes the combination of two zener diodes (Z1, Z2), a resistor (R1), a capacitor (C1), and a gated diode switch (GDS) to facilitate the rapid discharge of high voltage transients.

Abstract: An all solid-state protector circuit utilizes the combination of four zener diodes (Z1, Z2, Z3, Z4), two resistors (R1, R2), two capacitors (C1, C2), and two gated diode type switches (GDSA, GDSB) and provides bilateral voltage surge protection.

Abstract: A clock generator (buffer) circuit, which consists of an inverter stage, three serially connected field effect transistors, a bootstrap capacitor, a delay element, and two totem pole stages, has good response time and is useful with many of today's static random access memories. The transistors used are enhancement and depletion mode insulated gate field effect transistors.

Abstract: A high voltage solid-state switch uses a dielectrically isolated lightly doped p- type semiconductor body with a heavily doped p+ type anode region, a heavily doped n+ type gate region, a moderately doped p type shield region, and a heavily doped n+ type cathode region. The shield region surrounds the cathode region. Separate electrodes contact the anode, gate, shield, and cathode regions. The gate and cathode regions also act as the collector-emitter output circuitry of an n-p-n transistor with the shield region acting as the base. With the shield (base) region forward-biased with respect to the cathode or gate regions, the n-p-n transistor is biased on and the collector and emitter are rapidly pulled close to each other in potential. With proper operating potentials applied to the anode and cathode regions, the switch rapidly assumes an "ON" state when the potential of the shield (base) region is set to a level which biases the n-p-n transistor ON.

Abstract: An improved field effect transistor sense amplifier uses a cross-coupled pair of first transistors (Q1, Q2) with separate third and fourth transistors (Q3, Q4) connected by the sources (12, 14) to each of one of cross-coupled terminals (12, 14) of the cross-coupled pair (Q1, Q2). Read circuitry (Q7, Q8) is connected directly to the cross-coupled terminals (12, 14) of the cross-coupled pair (Q1, Q2). Write circuitry (Q9, Q10) is connected to the drains (18, 22) of the third and fourth transistors (Q3, Q4).

Abstract: A solid-state protector circuit utilizes the combination of two zener diodes (Z1, Z2), a resistor (R1), a capacitor (C1), and a gated diode switch (GDS) to facilitate the rapid discharge of high voltage transients.

Abstract: A back gate bias voltage generator circuit consists of three MOS transistors (Q4, Q5, Q6) with a separate load element (Q1, Q2, Q3) coupled to the drain of each and a voltage clamp (Q7) connected to an output terminal (16). A terminal at the potential of a power supply (VCC) serves as one input and a terminal at the substrate potential (VSub) serves as another input. When the power supply (VCC) potential and the substrate potential are within normal operating ranges, the output terminal (16) assumes a reference potential (VSS). The potential of the output terminal increases in magnitude if either of the two input potentials (VSS, VSub) goes outside preselected operating ranges.

Abstract: A latching type of sense amplifier, which uses depletion mode transistors as resistive load elements, a pair of enhancement mode field effect transistors as input devices, two other pairs of enhancement mode field effect transistors, and, in addition, a cross-coupled pair of enhancement mode field effect transistors, provides relatively high sensitivity and fast latching time essentially independent of input and output capacitive loading.

Abstract: To switch a first gated diode switch (GDS) to the "OFF" state requires a voltage applied to the gate which is more positive than that of the anode or cathode and the sourcing of current into the gate which is of the same order of magnitude as flows between the anode and cathode. Control circuitry, which uses a second GDS coupled by the cathode to the gate of the first GDS, is used to control the state of the first GDS. The state of the second GDS is controlled by a branch circuit having a relatively modest current handling capability. An n-p-n junction transistor has the emitter and collector coupled to the cathode and gate, respectively, of the first GDS, and has the base coupled through a p-n-p transistor to the input terminal of the control circuitry. The n-p-n transistor facilitates a quick turn-on of the first GDS by rapidly bringing the potentials of the gate and cathode of the first GDS to levels which are close together.

Abstract: Voltage generator circuitry uses a first capacitor (Q1) that is selectively isolated from an output terminal (26) by a first transistor (Q4). The gate of Q4 is coupled to a circuit terminal (16) which is capacitively coupled via second capacitor (Q5) to the output terminal (20) of a delay gate (28). The first capacitor (Q1) is charged to a potential level near or at that of a power supply (VDD) and then a positive going waveform applied to Q1 causes it to be charged to a potential level above VDD. Terminal 16 is charged by the positive going waveform to a value at or near VDD and then it is increased in potential after the delay time of the delay gate (28). This enables (biases on) Q4 and allows the output terminal (26) to assume a potential level greater than that of VDD.

Abstract: A bipolar transistor structure consists of a standard structure and in addition consists of a low resistance-high impurity concentration region in the collector which contacts a nonactive portion of the base. The resistance between the base contact and the low resistance-high impurity concentration region of the collector, coupled with the capacitance between the two regions, results in the equivalent of a series R-C network between the base contact and the collector contact. The values of resistance and capacitance of this network are selected to insure "absolute" stability of the transistor when operated in a circuit.

Abstract: A low power high sensitivity detector having two pairs of MOS cross coupled transistors, voltage equalization circuitry, and a single input, with no external reference, forms the basic configuration of a detector-level shifter circuit which is compatible with today's single chip large capacity memories. The lengths of the channels of one of the pairs of cross coupled transistors are designed to be longer than the other pair. This provides a built-in imbalance which provides good tolerance to transistor parameter variation due to semiconductor processing variations.

Abstract: An input voltage overload protection semiconductor structure useful with MOS circuitry consists of a p-region in an n-substrate with p+ type regions formed on both sides of the p-region and an n+ type region centrally located in the p-region. Input signals are applied to the first p+ region. The gate of an MOS structure to be protected from voltage overload is connected to the second p+ type region. A power supply used with the MOS structure is connected to the n+ region. This structure provides significantly greater load protection than the standard resistor-diode-resistor circuit.

Abstract: A dynamic sense-refresh detector amplifier consists essentially of a cross coupled MOS transistor pair and two sets of load-refresh circuits which each include a capacitor and three MOS transistors. The load-refresh circuits eliminate the negative effect of threshold voltage losses on noise margin by allowing the memory cell from which information is read out and sensed to be refreshed to full 1 and 0 levels. A control terminal of a transistor of each load-refresh circuit is coupled to the transistor of cross coupled pair not associated with that load-refresh circuit. In addition, a voltage clamping transistor is used with each load device to further increase operating noise margins. The dynamic operation of the amplifier allows for relatively low power dissipation.

Abstract: Variations in threshold voltage of Metal-Oxide-Silicon (MOS) structures are attenuated by the inclusion in the fabrication process of a hydrogen anneal step using a temperature range of 650 degrees C.ltoreq.T.ltoreq.950 degrees C. This anneal step is designed to be the last step in the fabrication process which is performed at temperatures above 600 degrees C.

Abstract: A high speed bipolar transistor is obtained by the use of ion implanted compensating impurities into the base region near the collector-base junction. This compensating implant significantly reduces the base width of the transistor with little reduction in total base charge. This results in a transistor which is reproducible and has a higher frequency response than those manufactured using standard semiconductor fabrication methods.

Abstract: Many of the stacking faults which occur after oxidation of silicon wafers are substantially eliminated by the use of an argon-hydrochloric anneal of the wafers just prior to oxidation. This anneal, which is carried out in the same chamber in which oxidation is carried out, removes impurities from the surface of the wafers and thereby limits the sites at which stacking faults form after oxidation.

Abstract: A low-temperature, high-pressure, medium-power process, which utilizes a radio frequency powered radial flow reactor, utilizes only silane and ammonia as the reactant gases for deposition. The methods disclosed result in the deposition on semiconductor wafers of moderately high density silicon-nitrogen films which have low tensile stress and good crack resistance. In addition, these films provide good step coverage, good scratch resistance, and an inert barrier to sodium and moisture.

Abstract: An improved radio frequency (rf) powered radial flow cylindrical reactor utilizes a gas shield which substantially limits the glow plasma discharge reaction to a section of the reactor over the semiconductor substrates which are to be coated. The gas shield permits the use of higher rf input power which contributes to the formation of protective films that have desirable physical and electrical characteristics.