Patents Represented by Attorney Ishimaru & Associates LLP
  • Patent number: 8304922
    Abstract: A semiconductor package system includes providing a substrate having a plurality of thermal vias extending through the substrate. A solder mask is positioned over the plurality of thermal vias. A plurality of thermally conductive bumps is formed on at least some of the plurality of thermal vias using the solder mask. An integrated circuit die is attached to the plurality of thermally conductive bumps. An encapsulant encapsulates the integrated circuit die.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Sangkwon Lee, Tae Keun Lee
  • Patent number: 8304337
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a device over a substrate including a bond wire pad row located between a perimeter of the substrate and the device; configuring the bond wire pad row to include three sided bond wire pads that horizontally overlap; and forming an interconnection between the device and the bond wire pad row.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
  • Patent number: 8304296
    Abstract: A method of manufacture of a semiconductor packaging system includes: providing a substrate; mounting a semiconductor chip to the substrate; mounting a pillar ball having a ball height electrically connected to the substrate; mounting an interposer above the semiconductor chip and electrically connected to the pillar ball; and wherein: mounting the interposer or mounting the substrate includes connecting the pillar ball to a pillar base having a base height substantially less than the ball height of the pillar ball and the pillar base having vertical sides not covered by the pillar ball.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: November 6, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: ChanHoon Ko, Junwoo Myung, Wonil Kwon
  • Patent number: 8304919
    Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate having a transistor and a metallization layer; forming a metal pad in direct contact with the metallization layer of the substrate; forming a passivation layer in direct contact with the metal pad and covering the substrate; forming a routing trace above the passivation layer in direct contact with the metal pad, and the routing trace is substantially larger than the metal pad, and the routing trace is not electrically insulated by a subsequent layer; and forming a bump connected to the metal pad with the routing trace.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Rajendra D. Pendse, Chien Ouyang, Mukul Joshi
  • Patent number: 8303410
    Abstract: A method of operation of a navigation system includes: receiving a game search preference; locating a compliant opponent location conformant to the game search preference; identifying a first preference region encompassing the compliant opponent location; locating a noncompliant opponent location violating the game search preference; and adjusting the first preference region to exclude the noncompliant opponent location for displaying on a device.
    Type: Grant
    Filed: November 20, 2010
    Date of Patent: November 6, 2012
    Assignee: Telenav, Inc.
    Inventors: Yi-Chung Chao, HaiPing Jin
  • Patent number: 8304869
    Abstract: An integrated circuit package on package system includes: providing a lead having a wire-bonded die with a bond wire connected thereto; mounting a fan-in interposer over the wire-bonded die and the bond wire; connecting the fan-in interposer to the lead with the bond wires; and encapsulating the wire-bonded die, bond wires, and the fan-in interposer with an encapsulation leaving a portion of the fan-in interposer exposed.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Lionel Chien Hui Tay, Henry Descalzo Bathan
  • Patent number: 8304921
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a planar support structure having a cavity; forming a terminal within the cavity with the terminal coplanar with the planar support structure; forming a conductive pathway on the terminal and the planar support structure with the conductive pathway having a route portion and an interconnect attach portion at the end of the route portion; connecting a device and the interconnect attach portion with the interconnect attach portion towards the device; and forming an encapsulation over the planar support structure covering the conductive pathway and the device.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Allan P. Ilagan, Philip Lyndon Cablao
  • Patent number: 8306729
    Abstract: A method of operation of a navigation system includes: receiving a change request with a proposed change for an item; verifying a validity of the change request based on a confidence level meeting or exceeding a change threshold; and updating a target element of the item based on the validity of the proposed change for avoiding an incorrect update to the target element for displaying on a device.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: November 6, 2012
    Assignee: TeleNav, Inc.
    Inventor: Winston Yonglong Liu
  • Patent number: 8304286
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate assembly having a connection path; mounting a base device over the substrate assembly with a mount layer; mounting a stack device over the base device and having a stack die and a stack-organic-material; forming a stack-through-via in the stack-organic-material of the stack device and connected to the stack die and the substrate assembly; and applying a shield layer directly on a planarized surface of the stack-through-via partially exposed from the stack-organic-material.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Reza Argenty Pagaila, Dioscoro A. Merilo, Shuangwu Huang
  • Patent number: 8299595
    Abstract: A method of manufacture of an integrated circuit package system includes: forming a base package including: fabricating a base package substrate having a component side and a system side, coupling a first integrated circuit die to the component side, and coupling stacking interconnects to the component side to surround the first integrated circuit die; forming a stacked integrated circuit package including: fabricating a stacked package substrate having a chip side, coupling a lower stacked integrated circuit die to the chip side, and attaching on a coupling side, of the stacked package substrate, the stacking interconnects; stacking the stacked integrated circuit package on the base package including the stacking interconnects of the stacked integrated circuit package on the stacking interconnects of the base package; and forming a stacked solder column by reflowing the stacked interconnects.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: October 30, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: In Sang Yoon, SeongMin Lee, SangJin Lee
  • Patent number: 8299596
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a base device having a base circuit connector directly on the component side; attaching conformal interconnects, having the same pre-deformation height from the component side, directly on the component side and offset from the base device; and attaching a stack substrate having stack interconnects directly on the conformal interconnects, portions of the stack interconnects covered by the conformal interconnects having different deformation heights from the component side.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: October 30, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Rui Huang, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 8293584
    Abstract: An integrated circuit package system is provided including forming a wafer having a back side and an active side, forming a recess in the wafer from the back side, forming a cover in the recess, and singulating the wafer at the recess filled with the cover.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: October 23, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Dennis Guillermo, Sheila Rima C. Magno, Ma. Shirley Asoy, Pandi Chelvam Marimuthu
  • Patent number: 8288844
    Abstract: A method of manufacture of an integrated circuit packaging system includes forming a lead frame including providing a tie bar plate, forming conductive columns on the tie bar plate, forming a dielectric layer on the conductive columns, applying a conductive shield layer on the dielectric layer, and exposing the conductive columns through the dielectric layer and the conductive shield layer; forming a base package substrate; mounting a base integrated circuit die on the base package substrate; mounting the tie bar plate, over the base integrated circuit die, conductively coupled to the base package substrate to form the conductive shield layer into an electro-magnetic interference shield; and removing the tie bar plate to expose the conductive columns from the dielectric layer.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: October 16, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Rui Huang, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 8288860
    Abstract: An integrated circuit package system includes: providing a base package of an elongated rectangular-box shape containing first electrical circuitry and including: forming a rectangular contact strip on and adjacent to a first end of the base package; and forming a base contact pad on and adjacent to a second end of the base package for connection to an electrical interconnect.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: October 16, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Chee Keong Chin, Yu Feng Feng, Wen Bin Qu
  • Patent number: 8288205
    Abstract: The present invention is a method of manufacture of a package-in-package system, comprising: providing a bottom internal stacking module incorporating a semiconductor die and a package substrate, attaching an internal stiffening module, with a die receptacle, on the bottom internal stacking module, and attaching a top internal stacking module incorporating a further semiconductor die and a further package substrate upside-down on the internal stiffening module.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: October 16, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Seong Bo Shim, KyungOe Kim, Yong Hee Kang
  • Patent number: 8278148
    Abstract: An integrated circuit package system is provided including forming a leadframe having a frame and a die paddle having leads thereon. The leads are held with respect to the die paddle. The leads are separated from the die paddle, and a die is attached to the die paddle. Bond wires are bonded between the leads and the die. The die and bond wires are encapsulated. The leadframe is singulated to separate the frame and the die paddle.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: October 2, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Jairus Legaspi Pisigan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho
  • Patent number: 8278141
    Abstract: An integrated circuit package system includes: fabricating an integrated circuit substrate; forming an internal stacking module coupled to the integrated circuit substrate including: forming a flexible substrate, coupling a stacking module integrated circuit to the flexible substrate, and bending a flexible extension over the stacking module integrated circuit; molding a package body on the integrated circuit substrate and the internal stacking module; and coupling an external integrated circuit to the internal stacking module exposed through the package body.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: October 2, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Reza Argenty Pagaila
  • Patent number: 8273607
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 25, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Soo-San Park, Sang-Ho Lee, DaeSik Choi
  • Patent number: 8273602
    Abstract: An integrated circuit package system comprising: fabricating a package base including: forming a lead frame, coupling a first integrated circuit device under the lead frame, coupling a second integrated circuit device over the first integrated circuit device, and molding an enclosure on the lead frame, the first integrated circuit device, and the second integrated circuit device for forming an integration port; and coupling a third integrated circuit device on the integration port.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: September 25, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho, Jose Alvin Caparas
  • Patent number: 8274145
    Abstract: A semiconductor package system including: providing a substrate having a thermal relief thereon; depositing a mask on the substrate and the thermal relief, the mask deposited on the thermal relief and having a regular pattern to partially cover the thermal relief; and die attaching a semiconductor die over the thermal relief.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: September 25, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Leocadio M. Alabin, Librado Gatbonton, Chiu Hsieh Ong, Beng Yee Teh, Antonio B. Dimaano, Jr.