Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate with a face surface having a via therein and a back surface having a trench therein; filling the via with a conductive pillar; forming a recessed contact pad in the trench; filling the recessed contact pad partially with solder; and forming an under-bump metal having a base surface in electrical contact with the conductive pillar, and having sides that extend away from the face surface of the substrate and further extend beyond the base surface.
Abstract: An integrated circuit package system includes a base substrate, attaching a base die over the base substrate, attaching an integrated interposer having interposer circuit devices, over the base die, and forming a package system encapsulant having an encapsulant cavity over the integrated interposer on a side opposite the base die.
Type:
Grant
Filed:
February 2, 2007
Date of Patent:
June 12, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
Seng Guan Chow, Il Kwon Shim, Byung Joon Han
Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a horizontal ridge at a lead top side; forming a connection layer having an inner pad and an outer pad directly on the lead top side, the inner pad having an inner pad bottom surface; mounting an integrated circuit over the inner pad; applying a molding compound, having a molding bottom surface, over the integrated circuit, the inner pad, and the outer pad; and applying a dielectric directly on the molding bottom surface and the inner pad bottom surface.
Type:
Grant
Filed:
December 6, 2010
Date of Patent:
June 5, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
Henry Descalzo Bathan, Zigmund Ramirez Camacho, Dioscoro A. Merilo, Emmanuel Espiritu
Abstract: A mountable integrated circuit package system includes: mounting a first integrated circuit device over a carrier; mounting a substrate over the first integrated circuit device, the substrate having a mounting interconnect; connecting a first electrical interconnect between the carrier and the substrate; and forming a package encapsulation covering the carrier, the first integrated circuit device, the first electrical interconnect, and the substrate with the mounting interconnect partially exposed from and surrounded by the package encapsulation within a cavity of the package encapsulation.
Type:
Grant
Filed:
November 1, 2007
Date of Patent:
May 29, 2012
Assignee:
STATS ChipPAC Ltd.
Inventors:
Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua
Abstract: An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.
Abstract: An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.
Abstract: A method for manufacturing a package system includes: providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
Type:
Grant
Filed:
December 22, 2010
Date of Patent:
May 22, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
A Leam Choi, Young Jin Woo, Junwoo Myung
Abstract: An integrated circuit package-on-package system includes: mounting an integrated circuit package system having a mountable substrate over a package substrate with the mountable substrate having a mold structure; forming a package encapsulation having a recess over the package substrate and the integrated circuit package system. The present invention also includes: forming an anti-mold flash feature with an extension portion of the package encapsulation and constrained by the mold structure at the bottom of the recess, and partially exposing the mountable substrate in the recess with the anti-mold flash feature formed with the mold structure; and mounting an integrated circuit device over the mountable substrate in the recess.
Type:
Grant
Filed:
November 29, 2007
Date of Patent:
May 22, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua
Abstract: An integrated circuit package system includes: providing a substrate; coupling an integrated circuit to the substrate; mounting a shielding element around the integrated circuit; applying a conductive shielding layer on the shielding element; and coupling a system interconnect to the shielding element.
Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.
Type:
Grant
Filed:
May 18, 2007
Date of Patent:
May 15, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
Haengcheol Choi, Ki Youn Jang, Taewoo Kang, Il Kwon Shim
Abstract: A method for manufacturing an integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of the base package; mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed.
Type:
Grant
Filed:
June 30, 2010
Date of Patent:
May 15, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
Dioscoro A. Merilo, Antonio B. Dimaano, Jr.
Abstract: A radio frequency identification system includes: supplying a radio frequency identification tag including providing a radio frequency identification transponder and writing transponder content to the radio frequency identification transponder; and feeding the radio frequency identification tag for an assembly line.
Abstract: A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.
Type:
Grant
Filed:
December 30, 2006
Date of Patent:
May 15, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
Kambhampati Ramakrishna, Il Kwon Shim, Seng Guan Chow
Abstract: An integrated circuit package system is provided. A dual-type leadframe having first and second rows of leads is formed. A first row of bumps is formed on an integrated circuit chip. Solder paste is placed on the first row of leads, and the first row of bumps is pressed into the solder paste on the first row of leads. The solder paste is reflow soldered to form solder and connect the integrated circuit chip to the first row of leads, and the integrated circuit chip, the first row of bumps, the solder, and the leadframe are encapsulated.
Abstract: A method for managing information includes: forming a meta data structure containing first information; forming an application data structure containing second information; establishing an association between the meta data structure and the application data structure wherein the first information has the second information associated therewith using a server; and displaying the association on a display.
Abstract: A package on package system is provided including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein. The first and second substrates are mounted having the first integrated circuit at least partially nested in the recess.
Type:
Grant
Filed:
August 31, 2007
Date of Patent:
May 1, 2012
Assignees:
Stats Chippac Ltd., Stats Chippac, Inc.
Abstract: An integrated circuit package in package system includes: a base integrated circuit package with a base lead substantially coplanar with a base die paddle and having a portion with a substantially planar base surface; an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface; a package-stacking layer over the base integrated circuit package; and the extended-lead integrated circuit package over the base integrated circuit package including: an end portion of the extended lead, directly on the package-stacking layer, and the extended lead exposed by and extending away from the bottom of the side of an extended-lead encapsulation and bending downwards toward the direction of the package stacking layer with the substantially planar lead-end surface coplanar with the substantially planar base surface.
Type:
Grant
Filed:
June 22, 2011
Date of Patent:
April 24, 2012
Assignee:
STATS ChipPAC Ltd.
Inventors:
Tsz Yin Ho, Dioscoro A. Merilo, Seng Guan Chow, Antonio B. Dimaanor, Jr., Heap Hoe Kuan
Abstract: An integrated circuit package system includes a conductive substrate. A heat sink and a plurality of leads are etched in the substrate to define a conductive film connecting the heat sink and the plurality of leads to maintain their spatial relationship. A die is attached to the heat sink and wire bonded to the plurality of leads. An encapsulant is formed over the die, the heat sink, and the plurality of leads. The conductive film is etched away to expose the encapsulant and the bottom surfaces of the heat sink and the plurality of leads. Wave soldering is used to form solder on at least the plurality of leads. Multiple heat sinks and hanging leads are provided.
Type:
Grant
Filed:
October 13, 2005
Date of Patent:
April 24, 2012
Assignee:
STATS ChipPAC Ltd.
Inventors:
You Yang Ong, Cheong Chiang Ng, Suhairi Mohmad
Abstract: A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of the semiconductor chip through the substrate opening.
Type:
Grant
Filed:
November 14, 2005
Date of Patent:
April 24, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
You Yang Ong, Zurina binti Zukiffly, Saat Shukri bin Embong
Abstract: A mobile location sharing system comprising: enabling a sender wireless device to send a payload including a location descriptor and a list of target identifiers to a group of targets; identifying a preferred communication mode for each in the group of targets; selecting a transmission format for the preferred communication mode; and sending the location descriptor in the transmission format selected for each in the group of targets for audio-visual output.
Type:
Grant
Filed:
December 28, 2007
Date of Patent:
April 17, 2012
Assignee:
TeleNav, Inc.
Inventors:
Musiri Shrivathsan, Nicola A. Crane, Richard J. Yang