Abstract: A fuse detecting apparatus includes a detector, a calibrator and a logical operating unit. The detector includes a detecting switch module and a detecting latch. The detecting switch module generates an initial detecting result according to first and second control signals and a status of the fuse. The detecting latch stores a voltage level of the initial detecting result or maintains its originally stored voltage level according to the initial detecting result for generating a pre-calibrating detecting signal. The calibrator includes a calibrating switch module and a calibrating latch. The calibrating switch module generates a calibrating result according to the first and second control signals. The calibrating latch stores the calibrating result and generates a calibrating signal accordingly. The logical operating unit generates a calibrated detecting signal according to the pre-calibrating detecting signal and the calibrating signal.

Abstract: In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type.

Abstract: A trusted network connect (TNC) method based on tri-element peer authentication is provided, which includes the following steps. Platform integrity information is prepared in advance. An integrity verification requirement is predefined. A network access requestor initiates an access request to a network access controller. The network access controller starts a mutual user authentication process, and performs a tri-element peer authentication protocol with a user authentication serving unit. After the mutual user authentication is successful, a TNC client, a TNC server, and a platform evaluation serving unit implement platform integrity evaluation by using a tri-element peer authentication method. The network access requestor and the network access controller control ports according to recommendations received respectively, so as to implement mutual access control between the access requestor and the access controller.

Abstract: A storage device, a memory controller, and a data protection method are provided. The method includes when receiving a read command sent by a host, adopting a corresponding output flow rate limit to determine an operation that is executed on read data corresponding to the read command by the host according to location information included in the read command or a type of a transmission interface between the host and the storage device. The method also includes executing an interference procedure by the storage device to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host when identifying that the operation is a copy operation.

Abstract: A current sensing circuit including a current sensing unit, a feedback control unit, and a digital output unit is provided. The current sensing unit senses a current and generates a pulse signal according to at least one reference signal and at least one feedback signal. The feedback control unit is coupled to the current sensing unit and generates the at least one feedback signal according to a clock signal and the pulse signal. The digital output unit is coupled to the current sensing unit and outputs a digital signal according to the pulse signal. The digital output unit counts an amount of pulses of the pulse signal in a predetermined time period to output the digital signal, wherein the amount of pulses is positively correlated with a value of the current.

Abstract: A flash drive and a housing assembly thereof is provided. The housing assembly comprises a housing, a base and a rotating mechanism. The housing has a first opening, a second opening, and a space, the first opening is situated at a side surface of the housing, and the second opening is situated on a top surface of the housing. The base is used for accommodating a storage device which has a connecting member, the base is movably disposed in the space and has a slot facing the second opening. The rotating mechanism is disposed at the second opening and mounted to the housing, the rotating mechanism has a protrusion portion movably engaged in the slot. When the rotating mechanism rotates relative to the housing, the protrusion portion moves along the slot and drives the base to reciprocate between a first position and a second position.

Abstract: A head light or a fog light for automobiles and automobiles includes a housing provided therein with an optically reflecting surface and a heat-dissipating member that is formed with LED grooves for receiving LEDs therein. The LEDs are installed for an angle to enable the light of the LEDs to be directly irradiated on the optically reflecting surface in a certain angle and simultaneously, the light will be reflected by the optically reflecting surface and cast out through the transparent front lampshade. Thus, the light produced by the LEDs can be utilized to a maximum extent, able to enhance lighting effect of the LEDs.

Abstract: A pattern printing system and data processing method thereof are disclosed, which are suitable for printing patterns on printed circuit boards or data format rearrangement printing used in displays. The pattern printing method includes a process for interpreting scription data into matrix data, a procedure for modulating the print head resolution and the printing resolution, a procedure for interpreting and transmitting data commands, a procedure for rearranging memory data, and a procedure for firing data synchronously so as to achieve high-resolution printing and to continuously modulate any print data.

Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.

Abstract: A flash memory storage system including a controller and a flash memory chip is provided, wherein the controller is disposed with a rewritable non-volatile memory. When the controller writes a security data into the flash memory chip, the controller randomly generates a data token and generates a message digest according to the security data and the data token by using a one-way hash function, wherein the data token and the message digest are respectively stored in the rewritable non-volatile memory and the flash memory chip. Subsequently, when the controller reads the security data from the flash memory chip, the controller determinates whether the security data is falsified according to the data token and the message digest respectively stored in the rewritable non-volatile memory and the flash memory chip. Thereby, the security data in the flash memory chip can be effectively protected.

Abstract: A data receiver and a method for adjusting the same are provided. The data receiver has an equalizer, a clock data recovery unit, an equalizer controller, and a decoder. The equalizer compensates incoming signal according to a configuration, and outputs corrected signal. The CDR unit uses a clock to sample the corrected signal from the equalizer and generates phase information of the clock. The decoder decodes the raw data. Each cycle of the clock is divided into a plurality of phases, and the phase information indicates the one of the phases that the corrected signal sampled therein. In a testing mode, the equalizer controller applies a plurality of setup values to the configuration individually and records the phase information for tuning the configuration. Therefore, the accuracy of the equalizer is improved and the good signal quality is obtained.

Abstract: A data writing method for writing data from a host system into a flash memory chip is provided. The method includes configuring a plurality of logical page addresses, grouping the logical page addresses into a plurality of logical blocks, and recording the data dispersion degree of each of the logical blocks. The method also includes receiving write-in data from the host system, identifying a logical block that a logical page address to be written by the host system belongs to, and writing the write-in data into the flash memory chip according to the data dispersion degree of the logical block, wherein the data dispersion degree of each of the logical blocks is not larger than a logical block data dispersion degree threshold value. Accordingly, the method can effectively reduce the time for executing a host write command.

Abstract: A block management method for managing a multi level cell (MLC) NAND flash memory is provided, wherein the MLC NAND flash memory has a plurality of physical blocks grouped into at least a data area and a spare area, each of the physical blocks has a plurality of pages divided into a plurality of upper pages, and a plurality of lower pages with a writing speed thereof being greater than that of the upper pages. The block management method includes configuring a plurality of logical blocks for being accessed by a host, recording the logical block belonging to a frequently accessed block and executing a special mode to use the lower pages of at least two physical blocks of the MLC NAND flash memory for storing data of one logical block belonging to the frequently accessed block. Accordingly, it is possible to increase the access speed of a storage system.

Abstract: A chip package structure includes a circuit substrate, a chip, at least one bonding wire, and an adhesive layer. The circuit substrate has a bonding surface and at least one pad disposed on the bonding surface. The chip is disposed on the bonding surface of the circuit substrate and has an active surface away from the circuit substrate and at least one contact pad disposed on the active surface. The bonding wire is connected between the contact pad and the pad, such that the chip is electrically connected to the circuit substrate through the bonding wire. The bonding wire includes a copper layer, a nickel layer covering the copper layer, and a gold layer covering the nickel layer. The adhesive layer is disposed between the pad and the bonding wire and between the contact pad and the bonding wire and respectively covers two terminals of the bonding wire.

Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.

Abstract: A method for giving a read command to a flash memory chip to read data to be accessed by a host system is provided. The method includes receiving a host read command; determining whether the received host read command follows a last host read command; if yes, giving a cache read command to read data from the flash memory chip; and if no, giving a general read command and the cache read command to read data from the flash memory chip. Accordingly, the method can effectively reduce time needed for executing the host read commands by using the cache read command to combine the host read commands which access continuous physical addresses and pre-read data stored in a next physical address.

Abstract: A method for memory address arrangement is provided. Data of different Y coordinates is moved to operation units divided by different X coordinates, or data of different X coordinates is moved to operation units divided by different Y coordinates, so as to realize the function of simultaneously longitudinally and laterally reading and writing a plurality of batches of data, thereby preventing the limitation of only longitudinally or laterally reading and writing a plurality of batches of data.

Abstract: A driving method and a transreflective display apparatus are provided herein. In the driving method, a plurality of voltage-to-transparency curves are provided. An ambient light intensity of the display apparatus is detected for determining a display mode, wherein the display mode is either a transmissive mode or a reflective mode. Next, one of the voltage-to-transparency curves is selected according to the display mode and the ambient light intensity for driving the display apparatus. Therefore, by referring a proper voltage-to-transparency curve to drive the display apparatus, the display quality of the display apparatus can be enhanced.