Abstract: An integrated circuit (12) contains a serializing transmitter, including a phase locked loop (31) that supplies seven clocks (41) with different phases to a serializer circuit (32). The serializer circuit accepts 7-bit words at a parallel input (42), and outputs these words serially in an end-to-end manner on a twisted pair (17), as a clock signal. The serializer circuit also accepts 7-bit words on a further parallel input (43), and transmits them serially in an end-to-end manner on a twisted pair (18), as serialized data. The integrated circuit also includes a built-in self-test circuit (33), which can supply test information to the two parallel inputs of the serializer circuit, and which can monitor the two twisted pairs while the serializer circuit operates at high data rates typical of normal operation, in order to detect any errors introduced by the serializer circuit. The self-test circuit produces a single digital output (48) to indicate whether an error has been detected.

Abstract: The present invention provides a system for stress testing an oxide structure to determine that structure's reliability in overstress conditions. The present invention provides an overstress test structure (400) that comprises a first transistor (406), having a first terminal coupled to ground, a second terminal coupled to a control signal (402), and a third terminal coupled to a first end of a first resistive element (412). A first voltage source (414) is coupled to the second end of the first resistive element. A second resistive element (416) is intercoupled between the second end of the first resistive element and ground. A second transistor (418) has a first terminal coupled to the second end of the first resistive element, a second terminal coupled to the first end of the first resistive element, and a third terminal coupled to a first node (420).

Abstract: A voltage follower comprising a first field-effect transistor (MN1) whose gate forms the input of the voltage follower. Further provided is a second field-effect transistor (MN2) whose drain connected to the gate forms the output of the voltage follower. The sources of the two field-effect transistors (MN1, MN2) are connected to each other and to the drain of a third field-effect transistor (MN3) serving as current source and to the gate of which a predefined bias voltage is applied. The invention employs in addition a fourth field-effect transistor (MN4) whose source-drain path is circuited between the output of the voltage follower and the drain of the third field-effect transistor (MN3) and whose gate is connected to the gate of the third field-effect transistor (MN3). As compared to prior art voltage followers the voltage follower in accordance with the invention comprises a wider voltage range in which it can be put to use. This can be made use of e.g.

Abstract: A computing device (40) comprises an electrical circuit and a software application. A display screen (138) and an input device (140) are electrically coupled to the electrical circuit. The software application provides instructions to determine the number of significant figures for a number entered via the input device, and simultaneously display on the display screen the entered number along with the number of significant figures for the entered number, and/or the software application provides instructions to calculate a floating point answer for a mathematical operation entered for one or more numbers entered into the computing device, round the floating point answer to the proper precision or to the proper number of significant figures, determine the number of significant figures for the rounded answer, and simultaneously display on the display the rounded answer and its number of significant figures.

Abstract: A computer system (30) and method of operating the same to model worst case performances of an analog circuit is disclosed. The computer system (30) includes disk storage devices for storing a process parameter data base (32), design of the circuit (31), and program instructions for performing the modeling method (33). Under the control of the program instructions, the system computer (22) retrieves the process parameters and desired performances, and performs a designed experiment to determine a Jacobian matrix of the dependence of the performances upon the process parameters. Singular value decomposition of the Jacobian matrix provides a set of singular values and a rotation vector, from which the coefficients of a worst case vector of the process parameters for each of the circuit performances are then derived. The system computer (22) then applies the simulation to the worst case vectors, to evaluate the worst case performances of the designed circuit.

Abstract: A state machine interface that can be used with digital devices whose interface characteristics are not known in advance. This interface is completely programmable on a clock-by-clock basis. The interface consists of an output component, which can be either a control register or a data bus, and an input component that can be combined to provide various input/output (I/O) functions. The state machine interface of this invention makes it possible to interface with many type of application devices, whose interface characteristics and/or waveforms may not be identical or are not known at the time a particular state machine is designed.

Abstract: In accordance with an embodiment of the present invention a microprocessor in the horizontal phased lock loop reads the horizontal timing with respect to the sync input and provides an increment inch to the horizontal discrete time oscillator to make corrections in its timing to maintain lock to the sync input. The horizontal discrete time oscillator output is used to produce a pixel clock which drives the color discrete time oscillator in a color phased locked loop. A microprocessor reads a phase error between the color burst input and the color local oscillator frequency and writes an increment incsc to the color discrete time oscillator to maintain lock to the color burst. The horizontal phase locked loop adjusts inch that varies about nominal increment (nom_inch) by ?h. The feed forward error correction for the adjustment to the color discrete time oscillator is the nomimal increment (nom_incsc) and a feed forwarded scaled version of ?h.

Abstract: In a microprocessor, a method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: A method for measuring a test differential voltage across a first output and a second output of a transmitter integrated circuit device, the test differential voltage corresponding to a voltage across the first output and second output appearing while the device is providing an output while being subjected to a voltages applied across a resistor network connected to the differential outputs, the resistor network including first resistor having a value of Ra connected between the first output and a first voltage, a second resistor having a value of Rb connected between the second output and a second voltage, and a third resistor having a value of Rc connected between the first output and the second output.

Abstract: A method and apparatus for routing messages in a wireless network. Transmissions from all devices are synchronized. Each device is equipped with a routing unit that checks incoming messages for integrity, discards “corrupt” messages, compares non-corrupt messages to the last transmitted message, and applies a set of rules to determine when and what the device should next receive or transmit. The synchronized transmissions and integrity checking process detect true collisions, which occur when multiple transmitters have attempted to send different messages to the same receiver. The comparing process ensures that messages are transmitted only if not previously transmitted, thereby avoiding loop problems.

Abstract: The voltage outputs of a charge coupled device (CCD) are examined to determine the hot pixels. A black pixel is determined to be a hot pixel if the voltage level associated with the black pixel exceeds the voltage level of an adjacent (e.g., previous) pixel by a threshold. If the present black pixel is determined to be a hot pixel, a previous black pixel is substituted for a present black pixel in the computation of the offset. However, if the first black pixel is determined to be a hot pixel, the second black pixel is used in lieu of the first black pixel. The offset is iteratively adjusted by an amount proportionate to an error determined based on the black pixels. The adjustment may be clipped by a threshold to avoid bands in the image.

Abstract: The present invention is a method and system for managing memory in a communication device which operates in a shared access media environment. In one aspect of the invention, each incoming broadcast frame of data has an associated reference mask to indicate through which of a number of channels the frame of data is to be transmitted.

Abstract: An offset correction circuit which enables a designer to control the correction range irrespective of the amplification sought to be achieved to the image component of the input signal. The offset correction further enables the designer to perform offset correction to a low resolution. Both range and resolution can potentially be attained using only two stages thereby minimizing power consumption and also minimizing introduction of any undesirable components.

Abstract: An original rectifier circuit is used to rectify an input signal and the input signal is coupled to be provided to a terminal of a amplifier. The amplifier is implemented to generate a differential output and the two terminals providing the differential output are coupled as inputs to a replica rectifier circuit, having electrical characteristics similar to the original rectifier circuit. One of the outputs of the amplifier provides a measure of the power of the input signal.

Abstract: A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion stage includes a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

Abstract: A CDM clamp circuit integrated into the interface circuit it is protecting on an integrated circuit. Generally, the integrated CDM clamp circuit and interface circuit are adjacent to each other and share a common device element or component, thus eliminating the need for a metal interconnect. Because there is no interconnect, the parasitic resistance and inductance are also minimized or eliminated from the circuit, thus reducing or eliminating excessive voltage drop. Preferably, the CDM clamp circuit is integrated into the circuit that it is protecting by having the two circuits share the same silicon source region. In a preferred embodiment input circuit, the same diffusion region is the source of both the input transistor and its associated CDM clamp transistor.

Abstract: The present invention provides a solution for interleaving data frames, in a digital subscriber line system in which the data frames are divided into first and second codewords such that the first codeword comprises an even number of data bytes and the second codeword comprises an odd number of data bytes. With an interleaver depth (D) greater than a number of data bytes in the codewords (N), the codewords are written to a first matrix (51) in a predetermined manner (220), and read from the first matrix (51) in a predetermined manner (240 or 250) in which the data bytes of the codewords are delayed by a number of bytes. The codeword data bytes (defined by: B0, B1, . . . , BN−1) are delayed by an amount that varies linearly with a byte index, where byte Bi (with index i) is delayed by (D−1)×i bytes. Further, de-interleaving the interleaved data frames can be implemented by a reverse interleaving writing (340 or 350) and reading (320) in a second matrix (52).

Abstract: A driver (300) which meets wide common mode voltage requirements is provided. Output passgates (310) protect sensitive line driver circuitry (305) from extreme bus voltages; enabling/disabling circuits (315, 316) detect fault conditions to ensure the line driver is disabled when needed, and pull-ups (320) assist in line driver start up by preventing negative voltage conditions on the bus driven by the line driver.

Abstract: An apparatus for providing optical black and offset calibration for an array signal comprising a sequence of voltage levels corresponding to a sequence of voltage samples of charge coupled devices arranged in an array. The apparatus includes a correlated double sampler adapted to receive the array signal and provide as an output a modified array signal comprising a sequence of first corrected output voltage levels. A programmable gain amplifier receives the modified array signal and provides as an output an amplified modified array signal comprising a sequence of second corrected output voltage levels. An analog to digital converter receives the amplified modified array signal and provides as an output a sequence of digital values. A digital signal storage device stores a digital value corresponding to a desired optical black level.

Abstract: A low gain feedback compensation circuit is provided on an integrated circuit. The feedback compensation circuit is coupled to a step down power supply on the integrated circuit. The step down power supply is operable to receive an input voltage and to generate an output voltage based on the input voltage. The feedback compensation circuit includes a line regulation circuit. The line regulation circuit is operable to receive the input voltage and a reference voltage. The line regulation circuit is also operable to generate an offset voltage based on the input voltage and the reference voltage.