Abstract: An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels representing two bit values and having a predetermined input bit period, and sending output data signals corresponding to the input data signals. Glitches are detected in the input data signals by detecting reversals of signal level having a duration less than the input bit period. A glitch time value corresponding to the glitch duration is determined, and then a sampling clock rate is set at a rate determined from the glitch time value. The input data signals are sampled at the sampling clock rate to generate a sequence of input data samples. A voting number of input data samples are monitored and an output signal is provided, representing the value of a majority of the sequential input data samples.

Abstract: A low power input with hysteresis circuit provides input hysteresis (for instance, from supply voltage ranges of 0.8 volt to 5.5 volts), while reducing the high-current region and the overall power consumption of an electronic device. The present invention utiliizes resistors and feedback transistors to limit the “through current” of the device when it is switching, and to provide extra hysteresis to the input circuit. The hysteresis can be adjusted by altering the resistance of the resistors. The present invention provides a very large hysteresis, or may be slightly modified to supply very little hystersis while having little effect on propagation delays, as compared with conventional input circuits with similar hysteresis. Accordingly, the present invention reduces the high-current region and the power consumption of the device while providing the required hystersis on the input.

Abstract: A embedded overcurrent protection circuit within the PWM feedback controller (30) of a power converter (100) having an novel current limit detection function that minimizes the effects of the turn-on period of the power device (14) is disclosed herein. This power converter includes a current limit detection circuit (10–20) that is reset on the rising edge of the system clock in a first step. In a second step, the power device (14) that is turned on. In another step, a current detecting circuit (10–20) detects the drain-to-source voltage across the power device (14) and the output current generated thereby. A sense circuit (18) compares the output current detected with a first predetermined limit value in another step. When the output current is less than the first predetermined limit value, a step is conducted where the output current is regulated by modulating the pulse width of the signal sent by a driver (12) to the control node of the power device (14).

Abstract: Disclosed are methods and apparatus for isolating and driving a power supply or power amplifier circuit. The circuits and methods provide for using a modulated PWM input signal and its complement to drive one or more core-less transformers providing an isolated power supply circuit output signal reproducing the PWM input signal. Preferred methods of the invention are disclosed in which steps for receiving and modulating a PWM input signal and its complement are included. In further steps, the modulated PWM signal and its complement control an isolated output driver to provide a power supply circuit output signal reproducing the PWM input signal. Embodiments of the invention are disclosed in which a circuit is configured for receiving a PWM input signal, providing isolation, and outputting a PWM output signal. The circuits include modulators for modulating a PWM input signal and its complement.

Abstract: A filter driver (125) can communicate with the USB stack and controller and with the CardBay, CardBus, and flashmedia stack and controller. This can allow the use of a CardBay card in a CardBus socket in a manner that is transparent to the user.

Abstract: A system for loading data into a module to be used with a portable computer device and the data in the module activated by a wireless connection or from instructions from the teacher. The module may be part of a rechargeable battery pack that includes data storage, or a wireless communications module that is connected to the portable computer device. In an embodiment, the data module is incorporated into a rechargeable battery pack. Data to be sent to the wireless device is transferred via a wired connection first from the charging bay to the battery pack and then from the battery pack to the wireless device when the battery pack is attached.

Abstract: A system for processing the measuring signals from a sensor 12, including of a first micro-controller 10 having an input for the sensor data, a first memory 18, 19 and a first processor 16, and a second micro-controller 24 having a second memory 26, 30 and a second processor 27. A bus system 22 is provided that connects the first micro-controller 10 with the second micro-controller 24. The first memory 18, 19 stores data and instructions that are configured so as to be adapted to the sensor 12 and enable the conversion of the signals provided by the sensor 12 into data representing the variable to be measured. The first processor 16 executes the instructions stored in the first memory 18, and transfers the resulting data by way of the bus system 22 to the second micro-controller 24. The second memory 26, 30 stores sensor-independent data and instructions, which enable the processing, by the second microprocessor 27, of the data transferred by the bus system 22, representing the variable to be measured.

Abstract: An audio compensation system (20) for producing a sound compensated output signal (So). The system comprises a volume control circuit (24) for producing a volume-adjusted signal (Sic) by applying a volume adjustment to an audio signal in response to a volume setting, wherein the sound compensated output signal is responsive to the volume-adjusted signal. The system also comprises circuitry (26, 30, 32) for producing an amplified signal (Sifa) by amplifying a selected bandwith of signals in response to the volume setting. The sound compensated output signal is also responsive to the amplified signal.

Abstract: A digital communications system with a built-in apparatus for improving receive path performance in the presence of noise. An analog datastream is provided to a hardware receive filter that rejects signals lying outside a frequency spectrum of interest, while a hardware equalizer flattens the channel response. An analog-to-digital converter digitizes the filtered and equalized analog datastream into a digital bitstream, which is then filtered, further channel-equalized and demodulated. The system also includes a memory, an estimator unit, having a first input coupled to the memory and a second input coupled to a data input, and an output coupled to a compute unit. The estimator unit is adapted to providing estimates of signal power, channel noise and channel response. The compute unit, has an input coupled the estimator unit and an output coupled to the memory, and is adapted to computing a channel capacity based the selected combination of modem parameters.

Abstract: A method for providing context save and restore using a test scan chain is provided. The method includes dividing a scan chain (34) of digital logic components (24) into a plurality of sub-chains (42). A first data set is provided in the sub-chains (42). The sub-chains (42) are linked in parallel and to a hardware resource for executing an application. The sub-chains (42) are linked to a device memory (18). A first application is executed to update the first data set in the sub-chains (42). The first application is operable to use the hardware resource. The updated first data set is stored in the device memory (18). A second data set is restored from the device memory (18) to the sub-chains (42). A second application is executed to update the second data set in the sub-chains (42). The second application is operable to use the hardware resource.

Abstract: A graphing calculator (10) having a user interface that allows the user to easily select mathematical objects from the history screen and incorporate those objects as inputs. The user interface preferably includes a sub-expression selection mode that allows the user to manipulate a selection box over the desired mathematical object.

Abstract: A single capacitor (C) can be used for both readout and noise reduction in an imaging sensor. This dual-purpose use of the single capacitor is facilitated by a switching arrangement (?1-?5) which connects the capacitor to a low impedance node (n7, n41) during charge storage. The low impedance node is also used to drive a column readout line (Vout).

Abstract: A method and apparatus for compensating for offset and drift of offset in an amplifier circuit having metal oxide semiconductor transistors in an input stage thereof and including a node responsive to a bias to change the offset of the amplifier circuit. In one embodiment, an offset digital-to-analog converter provides a first programmable bias corresponding to an offset of the amplifier circuit. A drift digital-to-analog converter provides a second programmable bias corresponding to a drift of the offset of the amplifier circuit. The first programmable bias and the second programmable bias are combined and coupled to the node. In another embodiment, a first programmable offset/drift generator is provided, capable of sourcing a first bias to the amplifier node compensating for a first portion of the offset and a first portion of the drift of the offset of the amplifier circuit.

Abstract: The present invention provides a system (200) for controlling drive signal timing parameters of an output driver circuit (206). The present invention defines a driver circuit having an output interface (204), and a first transistor (222) coupled to a first voltage supply (230), a first control signal (232), and a first node (220). The circuit also has a first resistive element, coupled between the first node and a second node (234). A second resistive element (228) is coupled to ground. A second transistor (224) is coupled to the second node, to a second control signal (236), and the second resistive element. The circuit has a third transistor (244), coupled to the first and second nodes, and to a third node (240). A third resistive element (242) is coupled between the third node and the output interface. A fourth transistor (238) is coupled to the first and third nodes, and to the output interface.

Abstract: A method for the authentication of a transceiver unit with respect to a second transceiver unit, located at a distance to it. A first signal is transmitted via an aerial connected to the first unit, when second unit is located within the reception area of the first unit. The first signal is received by means of the second unit via an aerial connected to it, whereby, on the basis of the first signal received, a value is measured that characterizes the strength of the electro-magnetic field generated by the first signal at the location of the second unit. A second signal is transmitted via the aerial connected to the second unit that contains information relating to the magnitude characterizing the field strength; and the second signal is received via the aerial connected to the first unit, where, on the basis of the second signal received, a value is measured that characterizes the strength of the electro-magnetic field generated by the second signal at the location of the first unit.

Abstract: A circuit generating an output phase signal with an optionally variable phase shift relative to a reference phase. It includes an oscillator (10) outputting phase signals at n outputs, each of which differs in phase by ?=360°/n. These phase signals are applied selectively via multiplexers to a phase interpolator, at the output of which the signal changed in phase relative to a reference phase. The output phase signal is generated in a charging circuit in which a capacitor can be varied by signaling current sources ON/OFF with the aid of phase switches in accordance with the phasing to be produced for the output signal. To avoid jitter in the transition from one phase to another separating switches are inserted in the connection between the current sources and the charging circuit, these separating switches being controlled so that they are never open at the same time.

Abstract: An auto-ranging electricity meter circuit having multiple current signal paths. Each of the current signal paths are amplified by a different amount of gain, and then applied to an ADC. The ADC then converts each of the amplified signals at different gains in a continuous process. The system analyzes the different sets of samples to determine which is the most accurate to use. Advantages include improved accuracy of an electricity meter using a lower cost A/D converter.

Abstract: A SECAM decoder and an FM modulator therefor are disclosed, in which a demodulated color signal is provided to indicate deviations in the frequency of modulated color information from a nominal subcarrier frequency. The demodulator comprises numerator and denominator filters operating on the modulated color information, and a divider providing a ratio result by dividing the numerator filter output by the denominator filter output. The demodulator may include two sets of numerator and denominator filters offset in phase from one another, where one of the two sets is selectively employed in order to mitigate divide-by-zero problems. Also disclosed are methods for demodulating digitized FM color signals in a SECAM decoder.

Abstract: A handheld computing device (40) comprises a software application adapted to provide instructions to graphically display a vector on a display screen (48) simultaneously along with the numerical values for components of the vector. The software application may be further adapted to provide instructions to perform a vector math operation on one or more vectors, to allow a user to pick the vector for use in the vector math operation, concurrently while graphically viewing the vector on the display screen (48) simultaneously with its numerical values for components, and/or to allow a user to graphically input the vector by incrementing a vector component with an arrow key (101-104) on the input device (50), concurrently while graphically viewing the vector and vector changes on the display screen (48).

Abstract: The present invention provides an apparatus and system for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture for convergence of video, data and voice in an SOHO application using a DSL router. An ATM processor (120) enables traffic shaping, and operation and maintenance processing within a single module. The ATM processor (120) further includes a processor (114) which executes firmware from a program memory (110). A register block (116) is provided for communicating setup and teardown notification, and OAM configuration to the processor (114) and a connection state RAM (112) provides for communicating connection configuration in which this information is used by the processor (114) when performing the functions of switching, QoS, and OAM. Transmit scheduler hardware (118) is provided for the scheduling of ATM cell transmission and is configured by the processor (114).