Patents Represented by Attorney, Agent or Law Firm J. P. Violette
  • Patent number: 6230118
    Abstract: DOS application programs are accommodated when using a controllerless modem by providing a virtual device driver. The virtual device driver emulates UART to UART communications and handles interrupts by the DOS applications and by a hardware port managed by the controllerless modem. In one implementation, the virtual device driver shares a communications interface in common with 32-bit applications. In a communication system environment, DOS applications can participate in modem to modem communications with remote DTEs and with other devices using the services of the virtual device driver.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: May 8, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: James E. Bader, Scott Deans, Richard P. Tarquini
  • Patent number: 6215459
    Abstract: A video controller for controlling at least two video displays incorporates a video memory for storing first and second video frames of interleaved pixel data. A video memory controller connected to the video memory sequentially reads data for a first pixel from the first video frame and data for a second pixel from the second video frame. Each pixel data is in turn transferred to a look-up table connected to the video memory controller which converts the first and second pixel data to first and second display data. A selector coupled to the look-up table alternately routes the first display data to one video display and routes the second display data to the other video display.
    Type: Grant
    Filed: October 1, 1993
    Date of Patent: April 10, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Dayakar C. Reddy, Chester Floyd Bassetti, Jr.
  • Patent number: 6208325
    Abstract: An image displayed on a digital display such as a flat panel display is rotated while the same image is displayed on a cathode ray tube display in unrotated form. When image rotation is selected, the read address sequence into a frame buffer may be reversed and the bit read sequence may be reversed. Thus a frame of panel pixel data stored within the frame buffer of an external video memory may be scanned onto a flat panel to display a rotated image.
    Type: Grant
    Filed: October 1, 1993
    Date of Patent: March 27, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Dayakar C. Reddy, Modugu V. Reddy, Krishnan C. Dharmarajan
  • Patent number: 6201492
    Abstract: A method and apparatus are used to continuously convert a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information for controlling the ADC components to produce a digital sample of the analog signal on the specified physical channel. At least one looping bit and at least one depth bit are also stored in a register on the serial port. The depth bit indicates a number of logical channels in one data scan. At least that number of logical channels are stored in the register. In response to a command bit indicating conversion mode, a quantity of data scans is output on a serial output pin of the serial port interface.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: March 13, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Aryesh Amar, Bruce Philip Del Signore
  • Patent number: 6185173
    Abstract: A sampled amplitude read channel is disclosed for disk storage systems comprising a encoder/decoder for implementing a high rate channel code that codes out specific minimum distance error events of a trellis sequence detector by enforcing a particular code constraint. The trellis sequence detector comprises a state machine matched to the code constraint which effectively removes the corresponding minimum distance errors from the detected output sequence. Additionally, the channel code encodes redundancy bits into the write data for implementing an error detection code. The redundancy bits are processed during a read operation to generate an error syndrome used to detect and correct other dominant error events, such as the NRZ (+) and (+−+) error events. In this manner, the most likely error events of the trellis sequence detector are either coded out by the channel code constraint, or detected and corrected using the error syndrome.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: February 6, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Jay N. Livingston, William G. Bliss
  • Patent number: 6185175
    Abstract: A sampled amplitude read channel is disclosed for disk storage systems (e.g., magnetic or optical) comprising a sampling device for sampling the analog read signal emanating from the read head positioned over a disk storage medium, a channel equalizer for equalizing the signal samples according to a desired partial response, a trellis sequence detector for detecting a preliminary sequence from the equalized signal samples, and a post processor for correcting errors in the preliminary sequence, including errors caused by the channel equalizers correlating the noise in the read signal. The preliminary sequence detected by the sequence detector is remodulated into ideal partial response samples and then subtracted from the actual signal samples to generate a sequence of sample errors. The sample errors are then filtered by a sample error filter, and the filtered sample errors are correlated with error event sequences corresponding to the most likely error events of the trellis sequence detector.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: February 6, 2001
    Assignee: Cirrus Logic, Inc.
    Inventor: Christopher P. Zook
  • Patent number: 6185467
    Abstract: An adaptive, discrete-time sliding mode controller (SMC) is disclosed which detects and adapts to gain variations in the controlled plant. The overall control effort is generated by combining a linear control effort with a discrete-time sliding mode control effort generated by switching between gains in order to drive the system's phase states toward a sliding line trajectory. A sliding mode variable &sgr;k defines the position of the system phase states relative to the sliding line. The SMC controller is designed such that the sliding mode variable &sgr;k crosses the sliding line and changes sign at every sample interval. For the nominal plant gain, the SMC controller is also designed such that the magnitude of the sliding mode variable &sgr;k+1=−&sgr;k will remain constant (&sgr;k+1=−&sgr;k) and substantially constrained to |&sgr;k|=&Dgr;/(1+&lgr;) where &Dgr; and &lgr; are predetermined design constants.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: February 6, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Paul M. Romano, Louis Supino, Christopher T. Settje
  • Patent number: 6183122
    Abstract: A digital parallel multiplier having encoders for each segmented bit pair of the multiplier input data and which selects one of 4 coefficients, based on the sum of the bit pair, that are then applied to the multiplicand input data to form a plurality of factored multiplicands. The sum of the factored multiplicands is augmented by two additional bits for all but the last of the factored multiplicands and by a logic 1 bit. The two additional bits are a logic 1 followed by the inverse of the sign bit of the factored multiplicand and are placed in the next two significant bit positions after the sign bit of the factored multiplicand, and the logic 1 is in the position occupied by the sign bit of the factored multiplicands which has the least significant bit position of all of the sign bits of the factored multiplicands.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: February 6, 2001
    Assignee: Cirrus Logic, Inc.
    Inventor: Edwin De Angel
  • Patent number: 6184893
    Abstract: A method and system for filtering texture map data for improved image quality in a graphics computer system. The present invention is directed to a method and system for performing texture map filtering for reducing “flickering” and “sparkling” when rendering a relatively small graphics primitives using a texel map of relatively larger area and low color frequency. A footprint area is defined as the area of texel map space that is mapped into one pixel coordinate of display space. One embodiment of the present invention is particularly useful in texture mapping where the footprint area is larger than one. In this instance, during rendering, the change in texel map coordinates (e.g., du, dv) is large for a unit change in screen coordinates (e.g., dx, dy). When obtaining a texel at location (u, v), the present invention performs a color filtering of texels located at distances du and dv away from the texel at location (u, v).
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: February 6, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Goran Devic, Christopher W. Shaw
  • Patent number: 6178199
    Abstract: An extended V.8bis command sequence enables a DTE to configure a DCE for alternative configurations and for independent V.8bis protocol negotiations. The DCE can be configured by sending it an AT command sequence as part of an initialization string. In this way, legacy applications can use the full capabilities of modems without rewriting the legacy application code.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: January 23, 2001
    Assignee: Cirrus Logic, Inc.
    Inventor: Robert J. Miller
  • Patent number: 6172361
    Abstract: The method of mounting a semiconductor device 200 on a supporting structure 101, the semiconductor device having a surface 201 including a defined area 202 for receiving photons and a plurality of conductors 203/204 for establishing connections to the device. An aperture 301 is formed through the supporting structure, the aperture sized to correspond to a size of the defined area of the semiconductor device. Conductors 302 are formed on the supporting structure adjacent to the aperture in a pattern corresponding to the pattern of the conductors on the semiconductor device. The semiconductor device is mounted to the supporting structure such that the conductors on the semiconductor device contact the conductors on the supporting structure where the defined area of the semiconductor device is exposed to photons through the aperture.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: January 9, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Douglas Holberg, Brannon Harris
  • Patent number: 6167498
    Abstract: A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325. The system CPU initiates data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the graphics engine 325. In an alternate embodiment, the subsystem includes a subsystem master control unit or MCU to enable parallel or simultaneous operation of the Host XY unit and the graphics subsystem MCU.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: December 26, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Michael Kerry Larson, Timothy James McDonald
  • Patent number: 6163286
    Abstract: A high performance test signal generator uses a digital to analog converter which converts an N-bit digital signal, such as provided by a computer waveform generator or by a CDROM into an M-bit upsampled digital signal. The M-bit digital signal is applied to an M-bit digital to analog converter to produce an analog output signal. The analog output signal is sampled and fed back across, the discrete time/continuous time interface to the input of the conversion circuit. The test signal generator has very low power consumption yet meets very strict noise and linearity requirements. The test signal generator can be used for testing seismic sensors such as geophones or hydrophones.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: December 19, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Wai Laing Lee, Axel Thomsen, Lei Wang, Dan Kasha
  • Patent number: 6157205
    Abstract: A technique for reducing jitter on a data channel utilized for transfer of data between components disposed on the channel. Instead of coupling a ground of the channel directly to a ground network of a chip containing the data transferring device, an impedance between the channel ground and a substrate is utilized to minimize the jitter.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: December 5, 2000
    Assignee: Cirrus Logic, Inc.
    Inventor: Eric J. Swanson
  • Patent number: 6148048
    Abstract: A receive path implementation for an intermediate frequency (IF) transceiver is disclosed that provides increased signal processing integrity and accuracy with an efficient and improved design. A complex filter for a bandpass delta-sigma analog-to-digital converter (ADC) provides efficient complex noise shaping with a combination of real and complex filters. An automatic gain control (AGC) amplifier provides a constant bandwidth and zero variation phase shift for all gain levels. Clock adjust circuitry provides a clock signal with a jitter-free edge and a high percentage duty cycle. A fixed-gain input amplifier provides a matched input impedance. A method for choosing design specifications provides improved anti-aliasing properties.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: November 14, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Donald A. Kerth, Tod Paulus, Shyam S. Somayajula, Tony G. Mellissinos
  • Patent number: 6147631
    Abstract: A signal processing circuit includes a main input sampling structure with an integrator operational amplifier and input lines including a switched capacitor. The input lines have switched connections to input signal lines and reference signal lines. A replica sampling structure is used in combination with the main input sampling structure to eliminate or reduce signal-dependent current that is drawn from the input signal line and the reference signal line. The replica sampler includes buffered input lines and switched capacitor of the input sampling structure but the capacitors have switched connections to the reference signal lines such that the connections have opposite polarity to the connections of the reference signal line to the input sampling structure. The replica sampler eliminates or reduces signal-dependent current from the reference signal lines. Buffering of the input lines in the replica sampler eliminates or reduces the signal-dependent current drawn from the input signal lines.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: November 14, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Prabir C. Maulik, Philip John Crawley
  • Patent number: 6144513
    Abstract: A discrete time servo demodulation technique incorporated within a sampled amplitude read channel to demodulate embedded servo field information stored on a magnetic medium. The servo field information is transduced by a read head into an analog signal, and converted to a sequence of sample values in the read channel. The demodulation technique is responsive to the sample values and includes a discrete time peak detector for detecting servo data, and a discrete time servo burst amplitude detector for measuring the amplitude of servo bursts. Peaks are detected in the analog read signal by sensing a change of slope from the sequence of sample values. The peaks are qualified by polarity in that a peak is detected only if its polarity is opposite in sign from the previous peak. The servo burst amplitudes are measured by interpolating, rectifying, and accumulating the sequence of sample values corresponding to the servo bursts.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: November 7, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss, Richard T. Behems
  • Patent number: 6141169
    Abstract: A system and method for an amplifier control circuit is provided which does not require the use of a large off-chip or on-chip capacitor for achieving a low frequency coupling corner, while still effectively allowing AC coupling the data detection circuit. In addition, the input offset voltage to the amplifier may be compensated and the inherent random low frequency input voltages provided to the amplifier may be controlled or canceled. Further, the amplifier control circuitry includes a freeze capability which allows the control circuitry to halt all updates to the input offset/low frequency control circuit when the voltage input signal is interrupted. In addition low frequency control and offset compensation updates may be performed without causing large output signal glitches so that the integrity of the received signal will not be compromised. In a preferred embodiment the system and method may be utilized for data detection circuits utilized in conjunction with optical disks.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: October 31, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: David M. Pietruszynski, Jerrell P. Hein, William G. Bliss, German S. Feyh
  • Patent number: 6137533
    Abstract: A system and method of enhancing dynamic range in images is disclosed that increases the contrast in the resulting image without requiring an increase in the dynamic range of the analog-to-digital converter used to convert the analog image signals to digital information. The system and method disclosed achieve this advantageous result by providing per-pixel gain control circuitry and per-pixel gain selection circuitry. The analog image signal range is segmented into a number (N) of multiple levels, where N is selected to be the desired level of enhancement. Multiple analog gain (G1) levels and multiple digital gain (G2) levels are also provided. The analog gain (G1) is selected for each image pixel based upon the segment in which that pixel falls so that the signal levels may be increased for each segment to utilize the full range (R) of the analog-to-digital converter.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: October 24, 2000
    Assignee: Cirrus Logic, Inc.
    Inventor: S. Khalid Azim
  • Patent number: 6135651
    Abstract: A software patch method and apparatus using a content addressable memory (CAM) to produce a code change enable signal when a program memory address matches a patch memory address, to cause program execution of modem operation to be diverted to the patch code when an address comparison hit is achieved. The patching apparatus includes a program memory for applying program instructions onto a data bus for execution, unless an address comparison of a program address and a patch address causes application of a substitute address onto the data bus.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: October 24, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Karl Thomas Leinfelder, Wesley Hamilton Smith, Sanjay Gupta, Navin Jaffer, Shahin Hedayat, Babu Mandava