Abstract: A V.34 compliant modem uses a noise whitening filter to compensate for noise enhancement in an equalizer. The noise whitening filter uses a 3 tap FIR the response of which is determined by 3 coefficients. The coefficients are derived using a newly developed extension of the Levinson-Durbin algorithm to complex numbers. The coefficients thus derived are used to control the precoder as well as the noise whitening filter. The coefficients are also used to control precoding reconstruction after the decoder.

Abstract: A technique for providing a start-up circuit for a bandgap reference. An amplifier configured in a differential arrangement as the bandgap reference. A start-up circuitry ensures that a second input node is maintained at a lower voltage than a first input node of the amplifier at start-up, when the output node corresponding to the second input side of the amplifier is also pulled low.

Abstract: A graphics system including a selectable mode filter for improved texture mapping. An x, y pixel coordinate is mapped into a u, v texture map. The mapped u, v coordinate includes integer and fractional portions. Depending on the location of the coordinate relative to the four nearest texels, which are represented as integers, one of several texture mapping schemes are used to either select or calculate the texel value to be used to render the pixel at the x, y screen location. The three texture mapping schemes include point sampling in which the nearest texel from the texture map is selected, two-texel averaging in which the closest two texels are combined in a weighted average, and four-texel averaging in which the closest four texels are combined in a weighted average. By providing a selectable filter than can perform point sampling or two or four-texel averaging, the speed benefit of point sampling can be approached as well as the superior quality of two and four-texel averaging.

Abstract: A multi-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.

Abstract: A integrated circuit digital to analog converter converts an M-bit digital signal to an analog output signal. The analog output signal can be used to drive external devices such as an off-chip driver. The output of the external device is sampled and fed back across the discrete time/continuous time interface on the chip to the input of the analog to digital converter. Taking the feedback point after the external device ensures relatively high performance for noise and linearity using relatively low performance components, both on and off the chip.

Abstract: A digital to analog converter utilizes two discrete time processing stages, such as switched capacitor integrator circuits, operating at different sampling rates when converting the digital input signal to an analog signal. Use of two different sampling rates relaxes the requirements on antialias filters used in the continuous time processing.

Abstract: A digital to analog converter converts an N-bit digital signal into an M-bit digital signal and provides the M-bit digital signal to a conversion circuit which converts the M-bit signal to an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. An interpolation filter is used to increase the apparent sampling rate of the incoming N-bit signal.

Abstract: A 1-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.

Abstract: A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g.

Abstract: A technique for performing gain calibration on an analog-to-digital converter (ADC) in which offset errors are canceled during gain calibration. In an ADC having a differential integrator at the input of a modulator, two calibration measurements are obtained at the output, one based on a calibration input and the second based on the reversal of the input polarity. The two measured outputs are subtracted from each other so that offset errors introduced by the converter during gain calibration are cancelled.

Abstract: A phase comparator compares phase of a clock signal and a generated comparison clock signal based upon rising edges. The output of the phase comparator may include a series of short up (U) pulses or down (D) pulses, depending whether the phase of the comparison clock is leading or lagging the clock. Up and down pulses U and D control an up/down shift register which in turn compensates phase difference by inserting or removing additional discrete delay elements in a variable delay line. Based upon delay signals generated by the variable delay line, a double frequency clock generator generates a 2.times. clock signal. The 2.times. clock signal is divided by 2 in a divider to supply the phase comparator with the generated comparison clock signal. The feedback scheme helps the digital delay lock loop of stabilize after a few clock cycles without additional external control.

Abstract: A system and method for conversion of graphics from computer graphics formats to television formats is disclosed. More particularly, an improved scaling and flicker reduction system and method is disclosed for scaling personal computer (PC) graphics formats into different resolution television (TV) formats and for reducing flicker due to the conversion process of interlacing non-interlaced PC graphics to match interlaced TV formats. The scaling implementation reduces line buffer requirements by using a conditional scaling technique for converting graphics from a PC resolution format to a TV resolution format. The flicker reduction implementation provides a two-dimensional adaptive filter that selects between multiple filters so that different parts of an image may have different flicker reduction and different levels of trade off between flicker reduction and resolution.

Abstract: A technique for separating an operation of a digital stage into separate noise generation periods in order to time the generation of noise from the digital stage. The invention is utilized in a mixed-signal integrated circuit having analog and digital signals in which the timing of the noise generation ensures that noise is abated during an analog sampling event.

Abstract: Synchronization words, contained within a data transmission are detected by oversampling the incoming data transmission by a factor of M. Each of M samples are stored in a respective register on an ongoing basis and a receiver is activated to monitor the contents of all registers to determine if they contain a synchronization word. Commonly a plurality of registers may detect the presence of a synchronization word simultaneously. The one having the largest amplitude bit samples is selected and the receiver changes mode to monitor the output of that register while another receiver is activated to monitor all registers. This is particularly useful in detecting synchronization words or flags in data packets, particularly in modem to modem communications.

Abstract: An audio information processing subsystem 200 is disclosed which includes a stream processor 100 for simultaneously processing multiple streams of audio data. Processing subsystem 200 also includes a program memory 202 coupled to stream processor 100 for storing instructions for controlling processing system 200 and a data memory 203/204 also coupled to stream processor 100. Additionally, a direct memory access circuitry 208 is provided for controlling direct memory accesses to a selected one of program memory 202 and data memory 203/204.

Abstract: Digital-to-analog conversion circuitry 100 is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter 300 includes pre-selected number of delay elements 301 for receiving stream of data in the 1-bit format and outputting a plurality of signals in response. A switched capacitor digital-to-analog converter 106 forms a second portion of the finite impulse response filter 301 and has a plurality of elements each receiving one of the plurality of signals as selected to effectuate a set of filter coefficients, converter 106 summing the plurality of signals and outputting an analog data stream.

Abstract: A message is transferred from external device through a first processor and from the first processor to a second processor. A check is made that the message passed to the second processor without error. The message is interpreted by a selected one of the first and second processors. Boot operations are performed by the selected processor in response to the interpretation of the message.

Abstract: A method of concealing errors received in a stream of data by a multiprocessor system having a first digital signal processor for initial processing of incoming data and a second digital signal processor for processing data passed from the first processor. The method includes the steps of detecting an error in an incoming frame of the stream of data with the first processor, sending an error message from the first to the second processor, halting transmission of the remainder of the frame to the second processor, and processing a frame of dummy data with the second processor. The frame of dummy data is passed to a processing engine forming a portion of the second processor to maintain data pipelining. Interprocessor communications between the first and second processors is established by handshaking through an interprocessor communications register, wherein the first processor detects an error in a frame of data and sends a message to the second processor.

Abstract: A static, low-power differential sense amplifier (DSA) and method includes operation of cross-linked channels having complementary differential nodes separated from ground by corresponding parallel-transistor pairs. The DSA output channels have complementary output nodes separated from ground by corresponding parallel-transistor pairs. The DSA further includes logic gates to produce a sense amplifier output. Each logic gate is driven by a corresponding complementary differential node and an opposite complimentary output node. The DSA includes transistors activating a done line under control of the complementary differential nodes.

Abstract: A self-timed multiplier and method are disclosed together with an analog to digital converter (ADC), which reduces ADC latency without requiring large silicon areas for implementation. The self-timed multiplier may be utilized by delta-sigma ADCs to perform gain compensation multiplications at the end of convolution, or may be used by other ADC designs or ADC systems for multiplications required during each convolution. The self-timed multiplier utilizes cascaded adders that produce completion signals to isolate the operation of the self-timed multiplier from the system clock of the ADC. The multiplier disclosed provides a self-timed, asynchronous circuit that will complete the desired multiplication in the time it takes for the required additions to propagate through the cascaded adders.