Abstract: A string set of series-connected incandescent bulbs adapted to being connected to a source of alternating-current operating potential and in which all of the bulb filaments in the set are individually provided with a non-avalanche shunt circuit which substantially maintains the rated voltage of the bulb across each of the bulb sockets whether or not an operative bulb occupies its respective socket and whereby the illumination of each remaining operative bulb continues to be substantially unchanged and substantially the same rated current continues to flow through said string set despite the absence of a plurality of bulbs from their respective sockets.

Abstract: An interactive overlay-driven computer display system wherein the selective activation of a software "switch" by the operator each time the digitizer stylus is contiguous to the overlay, causes a visual image of the overlay (which normally has selectable menu items printed thereon) to be automatically displayed on the monitor screen.

Abstract: A process for selectively forming NMOS/PMOS/CMOS integrated circuits and for selectively incorporating any or all of lightly doped drain-source (LDD) regions, sidewall gate oxide structures, and guard band regions.

Abstract: A keyboard system for chord entry keying of alphanumeric data fields includes decoding logic permitting substantially or near-simultaneous depression of numeric or alpha data keys and entry or function keys. The logic provides a decoding algorithm for resolving simultaneous entries by utilizing one or another rule of time of key depression. Depression of a numeric or alpha key within 60 milliseconds of an entry key is permitted for decoding of the data as the last key of the current data field. In a time frame between 60 and 100 milliseconds, a warning tone is received for purposes of verifying the last data field entry and to allow the operator to monitor timing performance.

Abstract: An electronic interface controller for coupling peripheral equipment, such as a keyboard, printer, or magnetic stripe reader, through a financial terminal to a financial computer system. The interface controller selects the peripheral equipment to be utilized, prescribes the operating mode, and establishes the timing and synchronization of the data transfer. Among its features the invention also includes a unique implementation of D-type flip-flops, with logic feedback, to create synchronous binary counters of selectable modulos.

Abstract: A fuse programmable ROM includes a wafer for a CMOS-type structure having an emitter, which emitter is overlain by a fuse pad of an undoped polysilicon and a conductive layer. There is a layer of barrier oxide disposed on the conductive top layer of the fuse pad and a sidewall oxide surrounding the periphery of the fuse pad both of which are overlain by the metallic electrical connection.The process of producing the fuse programmable ROM includes wide utilization of standard CMOS fabrication techniques with which are included the steps of depositing fuse material of undoped polysilicon, forming the fuse material into a fuse pad, and then making an electrical connection with the fuse pad.

Abstract: Disclosed is a nonvolatile memory device which utilizes a laser beam recrystallized silicon layer having source-channel-drain regions. Underlying the recrystallized layer and separated therefrom by a memory dielectric is a gate in alignment with the source and drain. The gate is formed directly on a substrate of an insulative material (e.g. non-silicon material).The process of forming the above device comprises forming a conductive polysilicon gate on a substrate followed by a memory nitride layer deposition thereon. A thick oxide layer is formed over the nitride followed by removal of the thick oxide corresponding to a central portion of the gate thereby exposing the nitride therebeneath. The exposed nitride surface is thermally converted into a thin, stoichiometric memory SiO.sub.2. A doped polysilicon layer is then formed on the structure and thereafter converted to recrystallized silicon by subjecting it to laser radiation.

Abstract: An addressing and control system for a mass memory which is partitioned into selectable pages of individually specified size. The invention generates a composite address for the mass memory so that a microcomputer of limited address size can access the mass memory by individually specified page. One circuit implementation utilizes a register to latch page size and selection information for subsequent combination with address information to generate a full address for the mass memory. In that situation, the size register multiplexes the address bus information and page selection information to maintain correspondence between the specified size of the page and the total addressing bits available. In another form, the invention provides for supplementing the number of address bus bits with bits transmitted over the data bus to extend the bit length of the address used to access the mass memory.

Abstract: An apparatus and method for scanning a document image in an m.times.n matrix. The device includes a sensing array for sequentially sensing along a scan line, elements along one dimension of the matrix, registers for sequentially storing sensed elements for a selected number of scan lines, and a circuit for effecting a scan line delay between sequential scan lines. Registers are also provided for effecting an element delay in all of the stored scanned lines along the other dimension of the matrix wherein the element delay is responsive to a sequential sensing of a matrix element. Selected matrix elements are combined with selected weighting factors for enhancing the document image being scanned.

Abstract: A process for fabricating silicon-on-insulator structures on semiconductor wafers and planarizing the topology of the patterns formed from the silicon. In the composite, the process provides for the formation of monocrystalline silicon islands electrically isolated by dielectric in substantially coplanar arrangement with surrounding dielectric. According to one practice of the process, substrate silicon islands are initially formed and capped, and thereafter used as masks to direct the anisotropic etch of the silicon substrate to regions between the islands. During the oxidation which follows, the capped and effectively elevated silicon islands are electrically isolated from the substrate by lateral oxidation through the silicon walls exposed during the preceding etch step. The capped regions, however, remain substantially unaffected during the oxidation. With the electrically isolated silicon island in place, a silicon dioxide layer and a planarizing polymer layer are deposited over the wafer.

Abstract: A read-only memory array formed from a multiplicity of NAND-organized FET stacks which are arranged in pairs and connected in alternate succession of adjacent pairs at opposite ends. Selection of stacks by pairs is performed by connecting the common node of four stacks at one end to a bit line and the common node of another four stacks, only two being common with the former four stacks, to ground potential. Selection between adjacent stack pairs is performed by bank select FETs in each stack. Each stack is precharged at both ends prior to selection. A sense amp is utilized to compare the current sinking capacity of the selected bit line with a reference stack, the difference being detected in a differential amplifier. A programmable output driver provides an adjustable rate of change in the output signal for step input signals.

Abstract: Arbitration as provided in two separate levels, first between two signals that may contend for access to a system resource, such as a memory, and second between the winner of the first arbitration and another source, such as a refresh signal timer, that must have access to the system resource periodically and independently of requests for access from the other signals. The winning signal of the first arbitration is not continuous but is divided into intervals, and the refresh timer gains control of the second arbitration at the end of each interval of control by the winning signal from the first arbitration.

Abstract: A device for focusing a laser on a recording medium by wavelength modulation is disclosed wherein the device includes a radiation source for providing a radiation beam of controllable frequency, a hologram intercepting the radiation beam for focusing the radiation beam as a function of its frequency, and a control system coupled to the radiation source for controlling the frequency of the radiation beam so as to focus the beam on a desired plane. The control system includes a sensor for detecting the focus of the radiation beam on a desired plane, and means for controlling the frequency of the radiation beam from the radiation source responsive to the detected focus.

Abstract: A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus.

Abstract: A virtual address and access protection code stored at that address are fetched simultaneously from secondary memory and stored in corresponding locations in first and second content addressable memories. When a program-generated virtual address is later applied to the first content addressable memory, corresponding access code is simultaneously applied to the second content addressable memory. Match signals obtained simultaneously from corresponding locations in both content addressable memories are combined to produce an access control signal to control access to data stored at a real memory address corresponding to the matched virtual address.

Abstract: To prevent a race in an asynchronous state machine branching from one state to either of two others, depending on which of two control signals arrives first, one of the signals is latched in the state just ahead of the branching state. The branching then takes place in the branching state upon arrival of the other signal but in a direction determined by the value of the latched signal. If the latched value indicates a wrong order of arrival, the machine releases the original latched value and latches an updated value of the one signal and returns to the branching state. The looping, with unlatching and relatching, continues until the latched value causes branching to take place in the proper direction.

Abstract: This invention relates to an adapter for interprocessor communications and the method therefor. An adapter is included in a data processing system which has a plurality of central systems, each of the plurality of central systems having at least one serial channel control processor. The data processing system further has a dynamic channel exchange for providing switching logic thereby permitting each of the plurality of central systems access to a plurality of peripherals coupled to the dynamic channel exchange. The adapter is operatively connected to the dynamic channel exchange for providing communications between any pair of central systems. The adapter comprises a link control module which provides handshake control to perform message bit/byte synchronization and translation.

Abstract: A process for fabricating volatile and nonvolatile field effect devices on a common semiconductor wafer, and a unique composite structure for a nonvolatile memory device fabricated according to the process. A distinct feature of the process is the elimination of nitride from beneath any poly I layers while selectively retaining sandwiched and coextensive segments of nitride and poly II layers for the memory devices. In one form, the method commences with a wafer treated according to the general localized oxidation of silicon process, followed by a blanket enhancement implant and selectively masked depletion implants. The succeeding contact etch step is followed by a deposition of a poly I layer, a resistor forming implant and a patterned etch of the poly I layer. Thereafter, a first isolation oxide is grown, selective implants are performed to center the memory window, the memory area is etched, and the memory area is covered by a regrowth of a very thin memory oxide.

Abstract: A process for treating the interior surface area of a glass nozzle for use in an ink jet printer device. The process includes cleaning of the surface area with a hydrofluoric acid solution under controlled conditions, rinsing and then protecting the cleaned area with a blocking agent to prevent contamination by the atmosphere prior to use of the nozzle in a printer device. The disclosed process is useful in minimizing air bubble formation and lock within the nozzle during use, and in facilitating ejection or purging of such air bubbles as may become ingested by the nozzle during service.

Abstract: A redundant modular power supply having a plurality of modules including a redundant module is disclosed which includes an apparatus for testing for a fault in any of the modules of the power supply. The redundant module is provided with a margin terminal, which when receiving a command from the testing apparatus, causes the redundant module to output current. The testing apparatus periodically issues such commands to the redundant module, monitors the output of the redundant module, and indicates an error condition if the redundant module does not respond properly to the commands from the testing apparatus. If the redundant module outputs current when not commanded to do so, a failure of one of the other modules in the power supply is indicated. If the redundant module fails to output current when commanded to do so, a failure of the redundant module is indicated.