Abstract: An electronic circuit configured to pass relatively high voltage signals therethrough when enabled, and block both positive and negative signals when appropriately disabled. The features of the circuit are particularly suited for coupling write and erase voltages to a nonvolatile memory array while integrated on a common chip with the array. In one form, the circuit includes a two-phase pump, which upon being enabled draws a transient current from the high voltage input line and raises the voltage level on an internal capacitive node in closed loop fashion by effecting unidirectional transfers of charge between successive capacitive nodes. The elevated internal voltage provides a driving signal to a driving circuit which passes the high voltage on the input line to an output line without incurring threshold voltage losses.

Abstract: Disclosed is an automatic self-adjusting CCD activated video camera circuit for adjusting the various CCD channel offset and gain values to the desired levels by utilizing the channels' digitized internal black and white references. Two identical feedback loops are used for offset and gain adjustment, respectively. In the gain/offset adjust loop, the white/black reference is compared to a desired gain/offset set by jumpers or switches on the video camera board. A difference in these values causes a corresponding 10 bit counter to increase or decrease its value. The digital counter value is converted to an analog signal and is used to optimally modify the channel gain/offset.

Abstract: A process for fabricating a bipolar transistor with a thin base and an abrupt base-collector junction includes the steps of depositing a thin layer of polycrystalline or amorphous silicon base material in a single crystal collector region, while in-situ doping the deposited silicon with boron atoms, and thereafter, recrystallizing the deposited silicon layer by thermal-pulse annealing at a temperature high enough to effect recrystallization and solid phase epitaxial regrowth while low enough to minimize interdiffusion of dopants between the base and collector.The process further includes providing the transistor fabricated by the aforedescribed steps with an abrupt base-emitter junction. This is accomplished by depositing n.sup.++ doped polysilicon with a LPCVD process and thereafter thermal annealing the polysilicon.

Abstract: Various structural patterns of alignment keys particularly suited for aligning masks and wafers during the fabrication of semiconductor devices. Each alignment key includes an orthogonal arrangement of bar-shaped segments. The relative dimensions of the mask and wafer alignment keys ensure a partial overlap and coaxial positioning of the bar-shaped segments when the keys are fully aligned. Precise optical alignment of the mask and wafer keys is evidenced by visually perceived edge diffraction effects. The invention also encompasses a systematic method for aligning representative structural patterns.

Abstract: A high speed priority interrupt system which permits a microcomputer to service a plurality of peripheral units on a priority basis is provided. Interrupt address jump vectors corresponding to the routines for servicing the peripheral devices are stored in a read only memory and are selectively transferred to a program counter in accordance with a predetermined priority basis to allow the microcomputer to interrupt its program and service one or more peripheral devices requesting access to the microcomputer. The interrupt system minimizes the time required by the microcomputer for interruption of the current program, servicing of the peripheral units, and resumption of the interrupted program.

Abstract: A memory architecture for a single chip microprocessor or microcomputer in which instruction words have a greater bit length than the data words and the need exists for additional off-chip program memory. The instruction word lines from the off-chip program memory are coupled directly into the existing columns of a matrix on-chip, program memory ROM. Supplemental FETs are connected to selected rows and columns of the on-chip ROM and are operated in such a way that it is possible to either enable the on-chip ROM and decouple the off-chip instruction words, or to disable the on-chip ROM and couple the off-chip instruction words through the on-chip ROM.

Abstract: A unified process for fabricating CMOS and SNOS devices on a common wafer. The process provides for the formation of poly resistors and interconnects at multiple levels while eliminating residual silicon nitride from active devices excepting the nonvolatile SNOS type memory cells. Foremost, the process significantly reduces the number of masking operations while limiting the fabrication temperatures at stages after the formation of the memory device dielectric. In the preferred arrangement, the process prescribes the formation of p and n-wells, gate oxides over the wells, and a patterned conductive poly layer thereupon. By alternate photoresist masking, the source/drain regions in the respective wells are then doped to coincide with the corresponding poly layer patterns. Thereafter, the SNOS device operational characteristics are refined, a first isolation layer of silicon dioxide is grown, and the memory dielectric is sequentially formed.

Abstract: A pulse width modulated D. C. to A. C. inverter circuit includes a first set of MOSFETS operated at a line frequency for transmitting high frequency clock pulses to a second set of MOSFETS for outputting a D. C. signal derived from a D. C. source. The inverter is part of an uninterruptable power supply and is operated upon the failure of the line A. C. to supply A. C. signals to a load. The high frequency clock signals are modulated on the A. C. output of the inverter. Two separate and distinct power switching channels are provided with each channel supplying one half of the sine wave outputted by the inverter.

Abstract: A circuit for generating control signals used in detecting a power failure in an uninterruptible power supply in which the A.C. signals of the power supply are examined to output a first signal representing the zero crossing of the A.C. signals. This first signal is used to reset an oscillator whose output clock signals are synchronized with the frequency of the A.C. signals by a phase lock loop circuit. The clock output of the phase lock loop circuit operates a counter whose output count is used to address a programmable read-only memory which outputs binary bits to a digital-to-analog converter which in turn outputs a full wave rectified sine wave operating at the system frequency which is used as a reference to detect the occurrence of a power failure in the main source of A.C. power signals. A second control signal is generated indicating a power failure condition which is used in switching an inverter into the power supply for supplying A.C. signals to a load.

Abstract: A random sequence of 1's and 0's is generated by detecting excursions of a random noise signal above a certain positive voltage level, below a certain negative voltage level, and into an intermediate voltage range between the positive and negative levels. A 1 bit is generated each time the random signal shifts to a value above the first level and then into the intermediate range, where it must remain long enough to coincide with a clock signal. A 0 bit is generated each time the random signal becomes more negative than the second level and then shifts back into the intermediate range and remains there long enough to coincide with one of the clock signals. A signal generated at the end of each bit signal is used to clock that bit into a shift register. The same clocking signal also causes a counter to count a predetermined number of random bit signals and then to output the information stored in the shift register to a data bus for use as a random number signal.

Abstract: A method and apparatus for storing data in which the data is checked for an error without requiring the data to include an error correction code. Included in the system is a logic circuit for dividing a data word by a polynomial during the time the data word is being written into the primary memory unit resulting in the generation of a remainder which is stored in an auxiliary memory unit. When reading the data word from the primary memory unit, the data word is again divided by the same polynomial and the remainder compared with the remainder stored in the auxiliary memory unit. If the remainders match, no error was introduced during the storing of the data in the main memory unit. If the remainders do not match, an error is indicated. This system allows a data word to be stored in a main or primary memory unit without requiring the word to include error correction bytes.

Abstract: This apparatus is used for minimizing the performance degradation due to address translation in computer systems employing random access memory and paging. It translates initial addresses into real addresses utilizing addressable memory and substitute paging. It decreases access time by not translating virtual address bits that are also real address bits and by commencing memory access using the available real address bits as they are available.

Abstract: A control circuit to disable the operation of a semiconductor microprocessor memory device in the event of an unauthorized attempt to access the memory. A logic circuit generates a control signal in response to receiving a predetermined binary bit pattern of a plurality of chip select signals. The control signal enables the memory device for operation. If the binary bit pattern is not presented, the memory device is disabled for operation.

Abstract: An electret material is formed by the method which includes the step of passing a pair of electrical conductor elements along the surface of a dielectric material heated to a predetermined temperature. The conductor elements are supported between a pair of support members driven in a direction to move the conductor elements along the surface of the dielectric material for applying an electrical field to the material. A heating element positioned adjacent the surface of the dielectric material and movable with the conductor element heats an area of the dielectric material located between the conductor elements enabling the material to be polarized by the electrical field, thereby producing an electret.

Abstract: A method for producing a phase hologram having a high diffraction efficiency which includes treating a developed photographic material with a stop bath containing sodium sulfate, bleaching with a tanning bleach having a low pH value and fixing the bleached material in a bath containing sodium thiosulfate.

Abstract: The disclosed apparatus operates upon binary signals corresponding to a scanned image. The binary images are stored in a matrix as concentric windows of interconnected rows and columns. The binary signals contained in the rows and columns are summed and logically compared against the sums of binary signals in adjacent windows and if the sums and logical combinations do not exceed preselected amounts it is assumed that the binary signals within a particular window are spurious, and means are provided for cleaning these signals from the window. Incrementing the binary images that are stored in the matrix permit the total scanned image to be analyzed.

Abstract: The Bragg's angle deviation of volume-phase-gelatin holograms is corrected by increasing the water content of the developed hologram and then reducing the water content of the hologram until the Bragg's angle deviation is zero.

Abstract: A process for forming high performance npn bipolar transistors in an enhanced CMOS process using only one additional mask level. The bipolar transistor is formed using a low dose blanket implant to form the base in the substrate n-well, then applying arsenic-implanted polysilicon to form the emitter. The emitter formation involves forming a blanket polysilicon layer over the wafer, then using the additional photomask to confine the subsequent arsenic implant to the emitter, n.sup.+ and polysilicon contact regions, prior to application of aluminum metallization. The arsenic implanted polysilicon technique provides state-of-the-art bipolar processing as well as improved contact characteristics. The combined polysilicon-aluminum metallization improves step coverage, circuit reliability, and reduces the possibility of aluminum diffusion (spiking) through junctions.

Abstract: A sheet moving apparatus comprising: a track having first and second spaced side walls and a third wall therebetween to form a sheet receiving space therebetween; and a sheet feeder for moving a sheet towards the third wall and thereafter moving the sheet in a downstream direction along the track. The sheet feeder comprises a rotatable member having a surface positioned in the sheet receiving space and a rotary drive enabling the rotatable member and its surface to be rotated. The sheet feeder also includes a rotatable or pivotal member moveable between first and second positions with regard to the rotatable member, with the pivotal member having a roller member to cooperate with the surface of the rotatable member to move a sheet towards the third wall when the pivotal member is in the first position, and the rotatable member and its surface are rotated.

Abstract: A display device comprising a transparent substrate bonded to a portion of a printed circuit board forming the display envelope, the circuit board including a plurality of electrical conductors. A first portion of the electrical conductors has one end forming the cathode electrodes of the display and its other ends connected to electrical control elements mounted on the circuit board adjacent the display envelope. Anode electrodes of the display are mounted on the substrate and are connected to a second portion of the electrical conductors by metal connectors located within the display envelope. The second portion of the electrical conductors are also connected to the electrical control elements which control the operation of the display.