Abstract: A method and apparatus for correcting single bit errors in data stored in a first memory includes a dynamic shift register for dividing data by a polynomial during the time the data is being written into the first memory resulting in the generation of a remainder which is stored in a second memory. When reading the data from the first memory, the data is again divided by the same polynomial. The remainder generated by the second division is compared with the remainder stored in the second memory. If the remainders do not match, indicating an error was introduced into the data during storage or retrieval of the data in the first memory, the remainder stored in the second memory is shifted into the dynamic shift register and followed by the shifting of a number of zero bits into the shift register which is equal to the maximum number of bits in the data located in the second memory.

Abstract: Disclosed is a manufacturing method of forming silicon gate, self-aligned MOS-type devices having submicron dimensions. After forming the gate from a highly doped polysilicon layer using a mask, the structure is subjected to a low temperature (700-750 degrees C.) thermal oxidation. Due to enhanced oxidation rate of doped silicon surfaces, a very thick oxide layer over the polysilicon gate sidewalls and a relatively thin oxide layer over the source-drain regions of the substrate are formed. The mask over the polysilicon and the oxide layer over the source-drain regions is removed and source-drain implantation is accomplished followed by selective deposition of metal (e.g. tungsten) over the source-drain regions and the polysilicon gate.In an alternative embodiment of this process, after forming the highly doped polysilicon gate using a mask, lightly doped source-drain regions which are self-aligned and in registry with the gate are formed by ion implantation.

Abstract: A time-of-day counter having a plurality of register stages for counting system clock pulses and for providing signals indicative of the status of each of the register stages is coupled by a bus to a dynamic memory of the type requiring a refresh cycle. Logic means operatively coupled to the time-of-day counter operate to pass the signals present at the output of the time-of-day registers onto the bus as memory address signals so as to effectively utilize the output signals of the time-of-day counter to periodically address all portions of the memory and to provide a refresh signal as each portion of the memory is addressed.

Abstract: A method and apparatus for generating a negative or positive image from a single photographic medium. A source of radiant energy is projected onto a sheet of dielectric material heating the material to a polarizing temperature. A pair of electrical conductors are moved in a first direction along the surface of the heated dielectric material polarizing the material in the first direction. A photographic mask is then positioned over the polarized material and the radiant energy and the electrical field is again applied through the mask in a second direction to polarize certain portions of the material in the second direction. Projecting polarized light through the dielectric material and rotating the material during the projection produces a negative or positive image on the screen.

Abstract: A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus.

Abstract: Described is a piezoelectric drive element assembly for use in ink jet printer devices. The assembly comprises a piezoelectric drive element, which is characterized by a pair of electrodes spaced apart and thereby electrically isolated from one another on an external lateral face of the drive element. The assembly further includes a printed circuit board having holes through which the drive element is fitted, with the electrodes of the drive element being soldered to opposite sides of the printed circuit board.

Abstract: A matrix print wire solenoid used in a wire matrix printer and including an enclosure member releasably secured to one end of the solenoid by a spring member deformed by the outer surface of the enclosure member to pre-load the enclosure member and an energy absorbing member located adjacent the enclosure member. A plunger member to which one end of a print wire is affixed is located adjacent the energy absorbing member for engaging the member during the rebounding movement of the plunger member enabling the energy absorbing member to transmit impact forces to the enclosure and the spring members.

Abstract: A character recognition system is disclosed in which each row of a plurality of parallel rows of binary signals representing the configuration of an unknown character is sequentially compared to a plurality of templates, each representing a known character. Each of the rows of signals is compared to feature characteristics of the unknown character twice. The rows of signals are first shifted one signal position and compared. The signals are then compared in their original position to detect an unknown character which has been printed off-center. Only those rows of signals which are required to contain a feature characteristic of the unknown characters are compared. The resulting data is utilized by a data processor apparatus identifying the unknown character.

Abstract: A hand held character scanning system is provided in which logic circuits are responsive to the generation of digitized data signals representing the character scanned together with the background area adjacent the character to determine if the data signals represent the scanning of a complete character. The signals are also used to determine the directions of scan together with raising an interrupt signal to a processor which performs a recognition operation on the data signals generated.

Abstract: A method and apparatus for selecting the start of an unknown character sensed by a character recognition system. A multi-channel read head develops a plurality of analog waveforms which form the image of an unknown character sensed by the read head. After the analog waveforms have been digitized and rectified, static and dynamic threshold values are applied producing a multi-column binary bit map of the unknown character. The start of the character is detected when two adjacent rows of the bit map are found to have five consecutive binary bits representing a character. The end of the character is detected when the rows of the binary bits representing background data have a width which is inversely proportional to the width of the character detected. This information is used by a character recognition apparatus in locating the start of the character and the data generated during a character recognition operation.

Abstract: A method and apparatus for simulating custom chips to be used in a data processing system. Each chip is simulated by a chip simulator that includes a mother board and a plurality of baby boards mounted and interconnected on the mother board. Each baby board has circuit components mounted thereon for performing the circuit function of one cell of the chip. Chip simulators are interconnected in an interconnecting apparatus that supports the mother boards in parallel and spaced apart relation. Chip simulators that represent all of the chips found on a single printed circuit board in the system are interconnected at the interconnecting apparatus so that design errors which are only evident when the chips are interconnected can be tested for and detected prior to fabrication of the chips.

Abstract: A device for deciphering encoded information is disclosed which comprises logic elements which combine a key input to implement a predetermined set of boolean transformations thereby yielding a corresponding set of translation terms. The translation terms are subsequently combined with corresponding encoded information to yield deciphered information.

Abstract: A sensing circuit for determining the amplitude of an unknown impedance by comparing the voltage levels generated in a succession of current mirror circuits. In one form, the present circuit is connected to a ROM array comprised of FET devices having the potential of 2.sup.n different channel structures, impedances, to represent n different bits of data. When addressed, the selected ROM FET is coupled to a current mirror reference FET, whose commonly connected gate and drain electrodes are further coupled to a succession of 2.sup.n -1 current mirror FETs. Each of the current mirror FETs is connected in conductive series with an incrementally different impedance, the value of each impedance lying substantially midway between the 2.sup.n potential impedances possible in the ROM cell FET. The voltages on the current mirror FETs are individually compared to the voltage on the current mirror reference FET to generate a digital format representation of the relative magnitudes.

Abstract: A method and apparatus for displaying frames of information on a CRT screen which reduces the memory requirements of the system by representing the words used in the message frames and the horizontal and vertical relationships between the words as single symbols. The repertoire of words used to construct the messages is stored only once, along with the symbols, significantly reducing the memory requirements of the system.

Abstract: A memory addressing system includes an addressable memory provided with error checking and correction (ECC) circuits which include output latches adapted to latch corrected data read from the memory. An applied memory address is compared in a comparator with a previous memory address stored in an address latch and if a match is detected, a match signal is effective to inhibit the occurrence of the next memory cycle and to activate a decoder coupled to the output of the ECC circuits to cause transfer to the system bus of selected data from the ECC latches. If no match is detected, a memory cycle is initiated to access the desired data in the memory. A high-speed memory operation is thus achieved utilizing simple circuitry.

Abstract: A circuit for eliminating current transients in a switching circuit of an uninterruptible power supply having a main source of AC signals and an inverter for supplying AC signals from a DC source including gating device operated in response to receiving signals representing the failure of the main source of AC signals and the occurrence of a current transient in the AC output of the inverter. Operation of the gating device enables high frequency clock signals to synchronously energize a MOSFET which applies the AC output signals over the inverter to a load dissipating the current transients. The circuit includes a transformer operated by the high frequency clock signals to switch the MOSFET at a high frequency enabling the current transients to be eliminated in a minimum amount of time.

Abstract: An activity detector device detects the presence or absence of information transmission over a serial data link between a computer system and a peripheral device. If a presence of a data signal exists as determined by the activity detector, the data signal is transmitted through to the computer system. If an absence of the data signal exists as determined by the activity detector, the input transmission link is decoupled from the computer system by the activity detector and places an all ones signal on the input line to the computer system consistent with the I/O protocol.

Abstract: A circuit board is utilized to hold a plurality of ink droplet producing elements in compact manner and conductive portions of the board are connected to actuate the elements in pulse-on-demand type printing.

Abstract: An FET comprising as many as three parallel channels having different threshold voltages. The two outer channels can have very low W/L ratios and resulting low drain-to-source currents. In one embodiment, the FET has a central enhancement channel flanked by low W/L ratio, low current, depletion channels. The FET is fabricated by forming an oxide mask (e.g., by etching a window in the gate oxide over the device active area); enhancement implanting the substrate through the window (e.g., n-substrate and n-implant for a p-channel FET); enlarging the window width a predetermined distance by etching; and depletion implanting the substrate through the window (p-implant for n-substrate) to a concentration below that of the enhancement implant. The gate structure is formed over the combined enhancement and depletion channels and a source and a drain span the ends of the channels. This effectively provides an enhancement FET which is in parallel with a depletion FET.

Abstract: Disclosed is an on-chip, dual polarity high voltage multiplier circuit consisting of a main high positive voltage multiplier and high negative voltage multiplier and an auxiliary high negative voltage multiplier coupled to the main multipliers to prevent turning on of parasitic transistors associated with the MOS diodes of the main multipliers and thereby extend the operating temperature range to 150.degree. C. and improve the fall time of the dual polarity multiplier. The auxiliary multiplier may be located in a common p-well with the main positive and negative multipliers or with the main negative multiplier and its output voltage is connected to this common well.