Abstract: A gray scale filter for image data is described which forces a least significant bit of a current pel equal to a most significant bit of the current pel when the most significant bit of the current pel is equal to the most significant bit of a previous and a next pel on a scan line of an image. The invention is embodied in a logic structure employing exclusive ORs to make comparisons between the previous, next and current pels and logic gates to gate the value of the most significant bit of the most current pel to an output representing a filtered least significant bit of the current pel. It should be noted that the value of the most significant bit of the current pel is not changed since only changes between gray-white and white or gray-black and black are filtered by the present invention.

Abstract: Apparatus and method are described for filtering noise from digital video images including means for determining first difference values between intensity values of current pel and one or more preceding pels, means for determining second difference values between intensity values of the current pel and one or more succeeding pels, means for limiting any of the first and second difference values that exceed a predetermined limit value, and means for generating a filtered value for the current pel by adding the intensity value of the pel to a scale summation of the limited first and second difference values.

Abstract: Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned.

Abstract: A method and apparatus predicting the outcome of a conditional branch instruction based on the previous performance of the branch, rather than on the instruction fields. The prediction of the outcome of a conditional branch instruction is performed utilizing a table that records the history of the outcome of the branch at a given memory location. A decode-time history table (DHT) is utilized. The DHT attempts to guess only the outcome of a conditional branch instruction, but not its target address. Thus, it can only be used to guess the branch outcomes at decode time when the target address is available. During the decoding of a conditional branch instruction, a table is accessed using the memory address of the branch instruction itself or some portions thereof. The table records the history of the outcomes of the branch at this memory location up to the congruence of the table size. A combinational circuit determines the guess (taken or not taken) from the branch history as provided by the table.

Abstract: A control system for interlocking processors in a multiprocessing organization. Each processor has its own high speed store in buffer (SIB) cache and each processor shares a common cache with the other processors. The control system insures that all processors access the most up-to-date copy of memory information with a minimal performance impact. The design allows read only copies of the same shared memory block (line) to exist simultaneously in all private caches. Lines that are both shared and changed are stored in the common shared cache, which each processor can directly fetch from and store into. The shared cache system dynamically detects and moves lines, which are both shared and changed, to the common shared cache and moves lines from the shared cache once sharing has ceased.

Abstract: A multiprocessing three level memory hierarchy implementation is described which uses a "write" flag and a "share" flag per page of information stored in a level three main memory. These two flag bits are utilized to communicate from main memory at level three to private and shared caches at memory levels one and two how a given page of information is to be used. Essentially, pages which can be both written and shared are moved from main memory to the shared level two cache and then to the shared level one cache, with the processors executing from the shared level one cache. All other pages are moved from main memory to the private level two and level one caches of the requesting processor. Thus, a processor executes either from its private or shared level one cache. This allows several processors to share a level three common main memory without encountering cross interrogation overhead.

Abstract: A Chinese/Kanji on-line recognition system consisting of four main sections, these being tablet electronics, a signal filter and segment integration unit, a base stroke classification unit and a symbol element recognition unit, and a symbol recognition output table. The tablet electronics provides pen coordinate signals and pen up/down signals which are applied to the signal filter and segment integration unit to define segments of strokes which correspond to continuous motion of a pen on a tablet in a fixed direction. The base stroke classification unit classifies the motion of the pen between pen down and pen up occurrences into one of 42 categories and also indicates if the stroke has crossed a prior stroke. This is then analyzed by the symbol element recognition unit which interprets the base strokes that have been recorded for the word and generates a sequence of symbol elements, referred to as "alphabet" components, that occur in this symbol.

Abstract: Apparatus for measuring fluid pressure and velocity, and in particular for maintaining an aspirator air velocity constant under varying atmospheric conditions. A precisely controlled air velocity is provided by a reference air source whose frequency is derived from a crystal oscillator. The total air pressure from the aspirator wind tunnel is compared with the total air pressure from the reference air source using a matched thermistor pair technique to convert the pressure difference into an electrical error signal which is used to control the main air source for the aspirator wind tunnel such that the error signal is maintained at zero, thereby maintaining the air velocity in the aspirator constant.

Abstract: A computing machine for concurrently executing instructions that have been compiled into a multi-instruction word comprised of a group of n instructions, where n is an integer. The group must not demand more than a predetermined number of data and instruction fetches, or more than one store operation. If a branch instruction occurs, it must always be at the end of the group. Each instruction utilizes a different set of data for purposes of instruction execution.

Abstract: The technique for transmitting address information between a processor and a plurality of memory subsystems in a common bus communication system. The width of the address field is greater than the number of lines on the bus. For example, addresses are three bytes wide, and the bus is one byte wide, thereby reducing the number of pins required on the processor and the subsystems. For communication between the processor and a given memory subsystem, only those bytes of a selected address which differ from the corresponding bytes of a previous address are transmitted sequentially for accessing a selected memory location.

Abstract: A character compaction and generation method and apparatus which is particularly adapted to the generation of complex characters such as Kanji characters. A dot matrix defining a given character is compacted into a sparse matrix, with the original character being reconstructed for printing or display from the compacted character defined in the sparse matrix. Each character in the complex character set is compacted and stored in memory one time only, with decompaction being performed each time a given character is to be generated. A set of symbols are defined to represent different patterns which occur frequently in the entire complex character set. Different combinations of the symbols define a given character. The information stored for each sparse matrix representing a given character is comprised of each symbol in the sparse matrix, its position, and its size parameter if the symbol represents a family of patterns which differ only in size.

Abstract: A portable hydraulic log splitter in which first and second splitting wedges are mounted in fixed positions relative to one another on a fixedly positioned supporting "H" beam. A ram is slideably mounted to the upper and lower flanges of the "H" beam for movement between the first and second splitting wedges. A two-way hydraulic cylinder means controls the ram for alternately forcing supplied logs against the first and second splitting wedges respectively. In a preferred mode of operation the two-way hydraulic cylinder means is comprised of first and second two-way hydraulic cylinder means disposed on opposite sides of the "H" beam and connected to the opposite sides, respectively, of the ram means for applying a substantially equal force to each side of the ram.

Abstract: A character compaction and generation method and apparatus which is particularly adapted to the generation of complex characters such as Kanji characters. A dot matrix defining a given character is compacted into a sparse matrix, with the original character being reconstructed for printing or display from the compacted character defined in the sparse matrix. Each character in the complex character set is compacted and stored in memory one time only, with decompaction being performed each time a given character is to be generated. A set of symbols are defined to represent different patterns which occur frequently in the entire complex character set. Different combinations of the symbols define a given character. The information stored for each sparse matrix representing a given character is comprised of each symbol in the sparse matrix, its position, and its size parameter if the symbol represents a family of patterns which differ only in size.

Abstract: A document scanner array which includes means for compensating for temporal changes in a light source, filters in the optical path, changes in the lens aperture and the like. The scanner array is comprised of a charge transfer device chip, which includes an exposure control section and a document information receiving section. A document holding means includes a reference indicia, with a reflection of the image of the reference indicia being imaged on the exposure control section simultaneous with the reflection of the document being imaged on the document information receiving section, in response to illumination from the light source. A common control signal concurrently applied to each section determines the time the reflected images are processed. The common control signal is terminated in response to the exposure control section sensing a given amount of light from the reflected image of the reference indicia.

Abstract: An image scanning system which alternately illuminates a charge transfer device with a focused, then defocused image of a line at a time of a document in order to provide comparison signals for binarization of the image concurrent with cancellation of dark current and sensitivity variations. The system includes focus-defocus, variable optical path length optical elements which are operated at a reduced speed by processing a line array at a time instead of a single picture element at a time in the image. A single charge transfer device chip comprises the scanner array, and includes a simple analog line memory comprised of light responsive elements, shift registers, gates, and a 1-bit comparator to perform the binarization. The charge transfer devices may be comprised of charge coupled devices (CCD) or bucket brigade devices (BBD) building blocks.

Abstract: There is described a droplet aspirator for an ink jet printer. The aspirator includes a housing having a tunnel therein, which is spaced from an ink jet nozzle which emits an ink jet stream which passes through the tunnel. A gas stream is also directed through the tunnel at substantially the same velocity as the ink jet stream for reducing the aerodynamic effects on adjacent ink droplets. The tunnels cross-sectional area is substantially constant from one plane to the next when measured in any given plane transverse to the longitudinal axis, for maintaining the velocity of the gas stream constant. The tunnel has a circular cross-section when used in a nozzle per spot system, and when used in an analog deflected system, has an entrance of one geometry, with the tunnel changing in geometry along its longitudinal axis to a different geometry at its exit. Preferably, in the analog deflected system, the entrance geometry is circular and the exit geometry is elliptical or rectangular.

Abstract: A method of and apparatus for time compression and changing the readout speed of a delta modulation encoded audio signal. The encoded audio signal has portions selectively deleted therefrom in accordance with detected zero crossovers of the same sign which occur in a predetermined timing sequence. The encoded audio signal which has had portions selectively deleted therefrom is decoded, with the undeleted decoded portions being joined. The undeleted portions have the same gain factor where joined, thereby eliminating step transients.

Abstract: A deformographic membrane display system in which a semiconductor substrate, for example silicon, has an insulating layer such as SiO.sub.2 formed thereon with an array of holes formed in the insulating layer. Alternatively, the insulating layer may be omitted, with the holes being formed in the substrate. A reflective membrane, including a thin metal layer, is formed over the surface in which the holes are formed. Electrodes are formed in the silicon substrate directly beneath or in each of the holes. Control circuitry, which for example, may be formed utilizing metal oxide semiconductor field effect transistor (MOSFET) technology and/or bipolar technology, is formed in the silicon substrate for selectively energizing the electrodes. The portion of the membrane over a given hole is deformed in response to the electrode thereunder being energized by the control circuitry.

Abstract: In a jet printing system which includes an array of N nozzles, the droplet streams emitted from at least the first and Nth nozzle are continuously guttered, and the droplet streams emitted from the other nozzles are one of selectively guttered or directed to a printing medium. Alternatively, the array may be comprised of N rows and M columns of nozzles. The droplet streams emitted from at least the first and Nth row, through the first through Mth column are permanently guttered, and the droplet streams emitted from the other nozzles are one of selectively guttered or directed to a printing medium. In each instance, the air flow created by the permanently guttered droplet streams reduces the aerodynamic retardation of the other droplet streams, thereby reducing the misregistration of the droplets on the printing medium. In one embodiment, the guttered droplet streams comprise a non-marking liquid such as water, and the other droplet streams comprise a marking liquid such as ink.

Abstract: An ink jet synchronization scheme, wherein the drop formation of respective streams in an ink jet array are synchronized acoustically by individual acoustic fiber inputs to each of the streams. The acoustic fibers are attached to grooves adjacent each of the nozzles, with acoustic isolation being provided between the fiber and the nozzle substrate to prevent direct excitation of the substrate. This prevents the occurrence of resonance within the nozzle plate. Alternatively, acoustic isolation is achieved by mounting the synchronization structure separate from the nozzle plate. For example, the acoustic fibers are attached to the charge electrode structure, or are attached to a support structure intermediate the nozzle plate and the charge electrode structure. The acoustic energy inputs to the fibers are independently controlled as is required for certain printing schemes or are made identical as is normally the case.