Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

Abstract: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate stricture.

Abstract: Modifying merged sub-resolution assist features includes receiving a mask pattern comprising the merged sub-resolution assist features, where a segmenting sub-resolution assist feature intersects a segmented sub-resolution assist feature at an intersection. Each sub-resolution assist feature is represented by an axis of the sub-resolution assist feature. The length of at least one axis is established, and an axis is modified in accordance with the length. Each axis is converted to a sub-resolution assist feature to yield the modified merged sub-resolution assist features.

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: An electrically erasable programmable read only memory (EEPROM) (500) is disclosed having improved data retention and read/write endurance. The EEPROM also lacks a more conventional cross coupling arrangement and thus is more area efficient than conventional EEPROM cells. The EEPROM (500) includes a PMOS transistor portion (514a) and an NMOS transistor portion (514b), where respective currents of these devices are compared to one another (e.g., subtracted) to give a differential reading that provides for the state of the EEPROM (500).

Abstract: Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second sub-resolution assist feature. A merge bar width of a merge bar is established. A distance between the first sub-resolution assist feature and the second sub-resolution assist feature is determined. A merging technique is determined in accordance with the distance and the merge bar width. The first sub-resolution assist feature and the second sub-resolution assist feature are merged according to the identified merging technique.

Abstract: The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.

Abstract: CMOS gate dielectric made of high-k metal silicates by reaction of metal with silicon dioxide at the silicon surface. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Abstract: A vertical thyristor for ESD protection comprises an anode (10), a cathode (16), a first gate electrode (12) and a second gate electrode (14). The first (12) and second (14) gate electrodes are arranged between the anode (10) and the cathode (16), wherein the first gate electrode (12) is an epitaxial silicon layer (20) formed upon the anode (10) and the second gate electrode (14) is an epitaxial silicon-germanium layer (24) formed upon the first gate electrode (12). The method of fabricating such a vertical thyristor comprises the steps of depositing an epitaxial silicon layer (20) upon the anode (10) and depositing an epitaxial silicon-germanium layer (24) upon the epitaxial silicon layer (20), wherein the epitaxial silicon layer (20) forms the first gate electrode (12) and the epitaxial silicon-germanium layer (24) forms the second gate electrode (14) of the vertical thyristor.

Abstract: According to one embodiment of the invention, a method for early qualification of semiconductor device includes performing initial testing on a semiconductor device, receiving fail data on the semiconductor device, determining a solution model for the semiconductor device based on the fail data, storing the solution model, performing subsequent testing on the semiconductor device, and comparing a result of the subsequent testing to the solution model.

Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

Abstract: A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method can include exposing the silicon to at least one of a hot ozonated sulfuric acid and a hot peroxide sulfuric acid to form the thick chemical oxide.

Abstract: The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for implanting charged particles in a substrate, among other steps, includes projecting a beam of charged particles (320) to a substrate (330), the beam of charged particles (320) having a given beam divergence, and forming a diverged beam of charged particles (360) by subjecting the beam of charged particles (320) to an energy field (350), thereby causing the beam of charged particles (320) to have a larger beam divergence. The method then desires implanting the diverged beam of charged particles (360) into the substrate (330).

Abstract: An SRAM memory cell structure utilizing a read driver transistor and a column select write transistor, and a method of operating the same. The SRAM memory cell comprises first and second cross-coupled inverters, having a first and second latch nodes, respectively. The cell further comprises a first write pass transistor connected between the first latch node of the first inverter and a first pass node, and a first wordline pass transistor connected between the first pass node and a first bitline. The cell also includes a first read driver connected between the first pass node and a source potential, and a control terminal of the first read driver connected to the second latch node of the second inverter.

Abstract: A set of memory cell test structures and a method for assessing of the static noise margin (SNM) of a memory cell or cells, using discrete point measurement structures provided either on-chip or within the scribe lines. A set of memory structures may comprise first and second test structures, individually comprising a memory cell, having one or more left and right half-bit test structures having hard-wired connections between select nodes of each memory cell half-bit and one or more voltage supplies. The half-bits of the first test structure are configured for measuring respective left and right standby SNM values, and the half-bits of the second test structure are configured for measuring respective left and right cell ratio values at respective output nodes of the structures, using applied supply voltages for on-chip assessment of the static noise margin of the memory cells.

Abstract: A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

Abstract: A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.

Abstract: In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer includes an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.