Patents Represented by Attorney Jacqueline J. Garner

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  • Semiconductor device having an implanted precipitate region and a method of manufacture therefor
    Patent number: 7361570
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor and an integrated circuit including the same. The semiconductor device 100, among other things, may include a substrate 110 having a lattice structure and having an implanted precipitate region 120 located within the lattice structure. Additionally, the semiconductor device 100 may include a dynamic defect 125 located within the lattice structure and proximate the implanted precipitate region 120, such that the implanted precipitate region 120 affects a position of the dynamic defect 125 within the lattice structure. Located over the substrate 110 in the aforementioned semiconductor device 100 is a gate structure 160.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: April 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Kaiping Liu
  • Method for controlling defects in gate dielectrics
    Patent number: 7351626
    Abstract: A method for improving high-? gate dielectric film (104) properties. The high-? film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: April 1, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Luigi Colombo, James J. Chambers, Mark R. Visokay, Antonio L. P. Rotondaro
  • Plateline driver with RAMP rate control
    Patent number: 7349237
    Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: March 25, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Sung-Wei Lin, Sudhir K. Madan, John Fong
  • SOI wafer with cooling channels and a method of manufacture thereof
    Patent number: 7344957
    Abstract: A method (100) of forming a silicon-on-insulator (SOI) wafer includes forming one or more channels in a top surface of a first wafer (104), and forming an insulator layer on a second wafer (106). The second wafer is treated (108) to generate a structural weakness therein, and the first and second wafers together (110) are then bonded together so that the channels face the insulator layer. A portion of the second wafer is then removed (112) from the bonded first and second wafers at a location corresponding to the structure weakness.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Gabriel G. Barna
  • Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity
    Patent number: 7344929
    Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions (150, 155) located over a substrate (110), the capping layer (210) having a degree of reflectivity, and annealing the transistor device through the capping layer (210) using photons (310), the annealing of the transistor device affected by the degree of reflectivity.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Manoj Mehrotra, Amitabh Jain
  • Laser scribe on front side of semiconductor wafer
    Patent number: 7344900
    Abstract: Disclosed are a semiconductor wafer (10) having a front side laser scribe (22) and the methods for manufacturing the same. The methods of the invention include the formation of a scribe foundation (12) on the front side of the semiconductor wafer (10) designed to accept laser scribing (22), and laser scribing the scribe foundation (12). Disclosed embodiments include a semiconductor wafer (10) having a scribe foundation (12) of layered dielectric (30) and metal (34) on the front side. According to disclosed embodiments of the invention, the formation of a scribe foundation (12) is performed in combination with the formation of a top level metal layer (34) on the semiconductor wafer (10) methods for manufacturing.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Byron Joseph Palla
  • Gate dielectric having a flat nitrogen profile and method of manufacture therefor
    Patent number: 7345001
    Abstract: The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Husam N. Alshareef, Rajesh Khamankar, Toan Tran
  • Staggered memory cell array
    Patent number: 7327591
    Abstract: A method of placing a cell in an array is disclosed. The method includes placing the cell a plurality of times (600, 602, 604) in a first array. The cell is also placed a plurality of times (606, 608, 610) in a second array. The second array is placed adjacent and offset from the first array by an offset distance (O2).
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: February 5, 2008
  • Multi-step process for patterning a metal gate electrode
    Patent number: 7323403
    Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: January 29, 2008
    Assignee: Texas Instruments Incroporated
    Inventors: Antonio L. P. Rotondaro, Deborah J. Riley, Trace Q. Hurd
  • Method for determining and classifying SRAM bit fail modes suitable for production test implementation and real time feedback
    Patent number: 7324391
    Abstract: A method (200) for determining various bit failure modes in a static random access memory device. A hard/soft bit failure test sequence is performed on each cell of the memory device to determine whether the cell exhibits a hard bit failure or a soft bit failure, then a data retention test is performed on the cell having soft bit failure to determine whether the cell exhibits a data retention failure. A write or disturb test sequence is then performed on the cell not having data retention failure, and a read or disturb test sequence is performed on the cell having write or disturb failure. Finally, a disturb test sequence is performed on the cell having read or disturb failure, and then an analysis is performed on the data from the tests to determine whether the cell exhibits one of a write, read, or disturb failure.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: January 29, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Wah Kit Loh, Md Abul Bashar Khan, Kemal Tamer San, Jon Charles Lescrenier
  • Refractory metal-based electrodes for work function setting in semiconductor devices
    Patent number: 7321154
    Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: January 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Luigi Colombo, James J Chambers, Mark R Visokay
  • In situ hardmask pullback using an in situ plasma resist trim process
    Patent number: 7320927
    Abstract: The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over the substrate 205 with plasma, trimming the photoresist layer 225 with a plasma to create an exposed portion 215a of the hardmask layer 215, removing the exposed portion 215a with a plasma to create a trench guide opening 227, and creating a trench 230 through the trench guide opening 227 with a plasma.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: January 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Juanita DeLoach, Brian A. Smith
  • Reliable high-voltage junction field effect transistor and method of manufacture therefor
    Patent number: 7312481
    Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: December 25, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
  • System for ultraviolet atmospheric seed layer remediation
    Patent number: 7312151
    Abstract: The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor substrate within. An ultraviolet radiation source (210) is disposed within the housing. A treatment medium (208) is also provided within the housing. The semiconductor substrate is enclosed within the housing and exposed to the treatment medium. The ultraviolet radiation source exposes the semiconductor substrate to ultraviolet radiation, desorbing the contaminants from the seed layer.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: December 25, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Aaron Frank, David Gonzalez, John DeGenova, Srinavas Raghavan, Deepak A. Ramappa
  • Method for improving reliability of copper interconnects
    Patent number: 7309651
    Abstract: Doping copper interconnects (100) with silicon (115) has been shown to improve Electromigration and Via Stress Migration reliability. After copper (118) is deposited by electrochemical deposition and chemically-mechanically polished back, doping is achieved by flowing SiH4 over the copper interconnect (100) for 0.5 to 5 seconds at a temperature of 325-425° C.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: December 18, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. West, Michael D. Barth, Steven P. Zuhoski
  • Ferroelectric memory with wide operating voltage and multi-bit storage per cell
    Patent number: 7304881
    Abstract: Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states may be written to and read from the ferroelectric memory device which are associated with a single polarization direction, thereby allowing for a single cell to contain more than one bit of data.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: December 4, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: John Anthony Rodriguez, Kezhakkedath R. Udayakumar
  • Gas switching during an etch process to modulate the characteristics of the etch
    Patent number: 7300878
    Abstract: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: November 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Ping Jiang, Francis Celii
  • Accelerated low power fatigue testing of FRAM
    Patent number: 7301795
    Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: November 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: John Y. Fong, Anand Seshadri, Sung-Wei Lin, Sudhir Kumar Madan, Jarrod Eliason
  • Work function control of metals
    Patent number: 7291527
    Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: November 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Mark Robert Visokay, Luigi Colombo, Antonio Luis Pacheco Rotondaro
  • One mask high density capacitor for integrated circuits
    Patent number: 7291897
    Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides electrical connection to the top electrode (112) of the decoupling capacitor (106).
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: November 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy A. Rost, Edmund Burke, Satyavolu S. Papa Rao