Abstract: An improved method and circuit for reduced settling time in an amplifier are provided. The amplifier comprises a composite amplifier circuit including a first amplifier configured with a second amplifier comprising an integrator circuit. The reduced settling time is facilitated through implementation of a faster path configured between an inverting input terminal of the second amplifier and an output terminal of the first amplifier for current needed by an integrator resistor due to any signal appearing at said inverting input terminal for said high-speed amplifier. The faster path can be realized through the addition of a compensation capacitor between the output terminal of the composite amplifier circuit and the inverting input terminal of the second amplifier. The compensation capacitor can comprise various values depending on any given number of design criteria.

Abstract: Disclosed are methods and systems for automatic gain control (AGC) in circuits. The disclosed methods and systems provide accurate and rapidly converging automatic gain control suited for video applications. According to disclosed preferred embodiments of the invention, a signal amplitude controlling method is responsive to gain underflow or overflow. A new fine gain control value is extrapolated and a new coarse gain control value is determined. The new fine gain and new coarse gain control values are applied to the signal to produce an output signal within a pre-selected output amplitude range.

Abstract: An automated test system (20) for testing a high-speed communications integrated circuit (10), such as a serializer/deserializer, is disclosed. The system (20) is able to test the parameters of receiver jitter tolerance and receiver sensitivity in a loopback connection arrangement, in which serial output terminals (SERTX) of the integrated circuit (10) are connected to serial input terminals (SERRX) of the integrated circuit (10). An attenuator (26), which in the disclosed embodiment includes programmable attenuators (30P, 30N) and a fixed attenuator (32), one of which is selected, is disposed in the loopback path. A deterministic jitter injector (28) is also in the loopback path, and may be implemented by way of variable length trace blocks (35P, 35N) on the test board (30).

Abstract: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.

Abstract: An apparatus for handling signaling between a sending device and a receiving device includes: (a) a buffering amplifier device having at least one input locus for receiving an input signal from the receiving device and having at least one output locus for presenting an output signal for the receiving device; each respective at least one output locus presents an output signal in response to the input signal received at a respective input locus of the at least one input locus; (b) a feed forward circuit coupling each respective input locus with its respective corresponding output locus to provide a feed forward signal to the respective corresponding output locus; the feed forward signal is in phase with the input signal received at the respective input locus.

Abstract: The object of this invention is to improve efficiency in the step-up/down mode and eliminate ringing in the output voltage when switching between the step-up mode and the step-up/down mode. This DC-DC converter has a local feedback control pre-processing circuit 12 arranged between voltage input terminal IN and one of the terminals of choke coil 10 or node Nx as well as an output feedback control booster circuit 14 arranged between the other terminal of choke coil 10 and the voltage output terminal OUT. Pre-processing circuit 12 has switching elements 16 and 18 and control circuit 20 that turns on/off switching elements 16 and 18 in a complementary manner. Control circuit 20 has error amplifier 22, reference voltage generating circuit 24, PWM comparator 26, inverter 28, and low-pass filter (LPF) 30.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a generally parallel configuration, each with inputs coupled through the same pair of matched input resistors which receive a differential input signal that may have both a positive and negative common mode range. An offset adjustment amplifier (17) receives a differential error signal representative of the difference between offset voltages of the first and second operational amplifiers and generates offset adjustment signals that are applied to input stages of the first and second operational amplifiers to adjust their respective offset voltages so as to equalize them.

Abstract: An amplifier (10?) has a first amplifier stage (14) for producing a control current (IX) in response to an input voltage. A second amplifier stage (16) has first (46) and second (38) transistors. The first transistor (46) is coupled to receive the control current (IX) and is operable to produce a control voltage. The second transistor (38) is coupled to receive the control voltage and operable to produce an output current. A nonlinear resistive element (50) is coupled to the first transistor (46) to add a nonlinear function of the control current (IX) to the control voltage. The nonlinear resistive element (50) may include a third transistor connected between the first transistor (46) and a reference potential, operable to receive the control current (IX) and to generate the nonlinear function thereof.

Abstract: A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a very low dielectric constant. Additional benefits are realized by electrically insulating the wires against short-circuiting, by cushioning the wires with a low modulus sheath, and by protecting chip bond pad metallization TABLE 1 Method of Moments Capacitance Models Wire Dimensions 25 × 25 microns Separation between Wires 63.5 microns Distance to ground ?191 microns Model Dielectric Self capacitance Mutual Capacitance constant of Wire 1 Wire 2 separation Model Dielectric Wire 1 Wire 2- Mutual cap constants self cap self cap pf/cm pf/cm pf/cm Plastic encased 4.0 1.03 0.54 1.57 package Cavity package 4./1.0/4. 0.31 0.12 0.43 Foam sheath 4./1./4./1./4. 0.34 0.16 0.50 wires/molded Wires - no 1.? 0.26 0.13 ?0.39.

Abstract: A voltage storage cell circuit includes an access transistor and a storage capacitor, wherein the source of said access transistor is connected to a bitline, the gate of said access transistor is connected to a wordline, and wherein the drain of said access transistor is connected to a first plate of said storage capacitor forming a storage node, and wherein the second plate of said storage capacitor is connected to a pump signal. This arrangement allows for a novel pixel circuit design with area requirements comparable to that of a 1T1C DRAM-like pixel cell, but with the advantage of an output voltage swing of the full range allowed by the breakdown voltage of the pass transistor. A spatial light modulator such as a micromirror array can comprise such a voltage storage cell.

Abstract: A circuit and method of dithering the switching frequency of an off-line power factor corrected (PFC) pre-regulator. The circuitry used to dither the frequency is advantageously accomplished by taking advantage of the PWM's internal timing circuitry. This invention reduces narrow band EMI and eliminates the need to provide specialty PWM controllers to achieve dithering.

Abstract: In order to minimize light diffraction along the direction of switching and more particularly light diffraction into the acceptance cone of the collection optics, in the present invention, micromirrors are provided which are not rectangular. Also, in order to minimize the cost of the illumination optics and the size of the display unit of the present invention, the light source is placed orthogonal to the rows (or columns) of the array, and/or the light source is placed orthogonal to a side of the frame defining the active area of the array. The incident light beam, though orthogonal to the sides of the active area, is not however, orthogonal to any substantial portion of sides of the individual micromirrors in the array. Orthogonal sides cause incident light to diffract along the direction of micromirror switching, and result in light ‘leakage’ into the ‘on’ state even if the micromirror is in the ‘off’ state. This light diffraction decreases the contrast ratio of the micromirror.

Abstract: A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing channels each of which has an analog input connected a different one of the stator coils and a channel output. Each of the processing channels includes a sigma-delta modulator with an output that supplies a bit-stream representative of an analog input signal received from a respective stator coil. Each channel also includes a first digital filter that receives the bit-stream from the sigma-delta modulator and converts the bit-stream to intermediate digital data-words. In addition, each channel has a digital synchronous demodulator that demodulates the intermediate digital data-words in synchronism with the carrier signal providing demodulated data-words.

Abstract: An amplifier system and method is provided for performing gate oxide integrity (GOI) testing of a power output field effect transistor (FET) of the amplifier system. The amplifier system and method provide for integrated test circuitry that protect drive components during overvoltage stress of a gate of the power output FET, and disables and/or isolates drive devices associated with leakage paths from the gate during gate oxide leakage measurements.

Abstract: An apparatus for use with a sensor includes first and second signal treating circuit segments coupled with the sensor for presenting a substantially balanced differential signaling representation of output signals from the sensor. Each respective signal treating circuit segment comprises a plurality of circuit elements having different electrical symmetries coupled in parallel and establishing a plurality of parallel signal paths having asymmetric signal handling characteristics. A feedback circuit is coupled with the first and second signal treating circuit segments and provides feedback signals to selected circuit elements in each of the first and second signal treating circuit segments. The feedback signals effect substantially balanced signal handling among the selected circuit elements having similar electrical symmetries.

Abstract: A low noise charge pump circuit includes a first terminal of a first flying capacitor selectively coupled to a first voltage during a first recharging phase and a second terminal of the first flying capacitor selectively coupled to a second voltage during the first recharging phase. The second terminal of the first flying capacitor is coupled to a precharge control circuit during a first parasitic capacitance precharging phase that occurs after the first recharging phase to cause the voltage of the first terminal of the first flying capacitor to equal an output voltage. The first terminal of the first flying capacitor is coupled to an output conductor conducting the output voltage during a first discharging phase that occurs after the first parasitic capacitance precharging phase.

Abstract: Processes for the removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the ability to accurately determine the endpoint of the removal step. A vapor phase etchant is used to remove a material that has been deposited on a substrate, with or without other deposited structure thereon. By creating an impedance at the exit of an etching chamber (or downstream thereof), as the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the endpoint of the removal process can be determined. The vapor phase etching process can be flow through, a combination of flow through and pulse, or recirculated back to the etching chamber.

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.

Abstract: Systems are provided for reducing electromagnetic emissions from a controller area network transceiver. A driver circuit is operative to transmit communications across an associated bus. A static driver replica circuit approximates a common-mode voltage associated with a dominant state associated with the bus. A receiver attenuator bias circuit forces a common-mode voltage associated with the driver circuit to be equal to the approximated dominant state common-mode voltage during a recessive state associated with the bus.