Abstract: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked.

Abstract: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.

Abstract: Described embodiments provide for an optical communications assembly or other optical assembly in which the post-dispersion optical signals are controlled in dispersive and non-dispersive directions. In one embodiment, the assembly includes an optical signal collimator configured to emit an optical signal based on an input communication signal. In addition, the assembly includes a dispersive device that receives the optical signal and disperses multiple wavelength channels of the optical signal in a dispersive direction. The assembly further includes a first light-directing device configured to control the dispersion of the multiple wavelength channels in the non-dispersive direction. A second light-directing device is provided to control dispersion in the dispersive direction.

Abstract: By allowing the block rate to vary, the existing Asymmetric Digital Subscriber Line (ADSL) system is modified to better address extended reach and higher data rates. A method is disclosed for providing improved reach from the ADSL standard by reducing the block rate from the ADSL standard and providing improved data rate for short loops by increasing the block rate from the ADSL standard.

Abstract: The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 110. RF plasma etching of the barrier material 200 that is deposited in the opening 140 occurs simultaneously with conducting the physical vapor deposition of the barrier material 200.

Abstract: Polyphase filtering, such as resampling for image resizing, on a processor with parallel output units is cast in terms of data access blocks and data coverage charts to increase processor efficiency. Automatic generation of implementations corresponding to input resampling factors by computation cost comparisons.

Abstract: A complementary-color-filtered array interpolation by first interpolate each color subarray so each pixel has four colors and then adjust each color at a pixel with addition or subtraction of a color imbalance factor for the pixel. For yellow and cyan the adjustment is subtraction but for magenta and green the adjustment is addition.

Abstract: A method of image compression with non-redundant complex wavelet transforms applied using a triband decomposition. Variant transforms for real and complex inputs allow for elimination of redundancy.

Abstract: A speech encoder/decoder for wideband speech with a partitioning of wideband into lowband and highband, convenient coding of the lowband, and LP excited by noise plus some periodicity for the highband. The embedded lowband may be extracted for a lower bit rate decoder.

Abstract: A method provides forward compatibility hooks for DFS and TPC for WLAN, so that the same mechanisms can be employed (with only minor changes/additions) for other regulatory domains, other bands, and/or other purposes. The current IEEE 802.11 h standard defines mechanisms for dynamic frequency selection (DFS) and transmit power control (TPC) that may be used to satisfy regulatory requirements for operation in the 5 GHz band in Europe. The present method provides a format to allow other bands, and relates to the supported channels element, channel switch announcement element, and the Basic/CCA/RPI histogram request/report. The method optionally reserves more than 3-bits in the Basic report (Map subfield).

Abstract: A method of image compression with wavelet transforms applied locally rather than globally by image component partitioning into independently transformed macroblocks plus overlapping data for filter length compensation.

Abstract: A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken target addresses for branch instructions, an execution pipeline (1740) with a branch execution circuit (1870), and storage elements (in 1860) and control logic (2350) operable to establish a first-in-first-out (FIFO) circuit (1860) with a write pointer WP1 and a read pointer RP1. The control logic (2350) is responsive to the branch prediction circuitry (1840) to write a predicted taken target address to a storage element (in 1860) identified by the write pointer (WP1) and the predicted taken target address remains stationary therein. The FIFO circuit (1860) bypasses a plurality of pipestages between the branch prediction circuitry (1840) and the branch execution circuit (1870). The control logic (2350) is operable to read a predicted taken target address (PTTPCA) from a storage element (in 1860) identified by the read pointer RP1.

Abstract: System and method for an optical position sensor architecture for use in servo systems. A preferred embodiment comprises a light source configured to produce a light with an intensity dependent upon a control signal, a first light sensor and a second light sensor positioned adjacent to one another, each light sensor configured to produce a current based upon an amount of light incident upon each light sensor. The preferred embodiment also comprises a slotted device coupled to the load and positioned between the light source and the first light sensor and the second light sensor. The slotted device regulates an amount of light striking the first light sensor and the second light sensor based upon a position of the load. The slotted device features a slot that has a radius with a linearly increasing radius as a function of rotation angle so that the optical position sensor has linear behavior.

Abstract: A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.

Abstract: An apparatus and method of synthesizing an output clock signal from a source clock signal. The clock synthesizer includes a phase generator, a phase selector, a phase interpolator, and control circuitry for controlling the phase selector/interpolator. The phase generator receives a high speed clock, and generates P phases of the source clock to define P phase sectors. The phase selector selects respective pairs of phases such that each pair bounds a respective phase sector. The phase interpolator introduces at least one phase of the source clock between each pair of phases to provide Q phases of the source clock within each sector. The phase interpolator uses the phases of the source clock to produce lagging (leading) phase shifts of 360/P(Q?1) degrees, thereby generating the output clock having a stepped up or stepped down frequency.

Abstract: A branch metric duplication method substantially reduces interconnection delays. The branch metric duplication method is particularly useful to implement a high speed radix-4 Viterbi decoder targeted for FPGA applications. The decoder includes a plurality of branch metric computation units (BMCUs), at least one add-compare-select unit (ACSU) having a plurality of cells, and a survivor path memory unit (SMU). The plurality of BMCUs, the at least one ACSU, and the SMU are configured to implement the decoder.

Abstract: According to one embodiment, a method for controlling positioning of an optical dithering element includes repeatedly driving the optical dithering element approximately between a plurality of desired positions by a generally periodic drive waveform. During a particular period of the drive waveform, the actual position of the optical dithering element is determined at a plurality of sample times. For each of the determined actual positions of the optical dithering element, a position error indicator is determined based upon whether the magnitude of the actual position is greater than, less than, or the same as a desired setpoint for the position of the optical dithering element. The method also includes generating an error signature for the particular period based on the determined error indicators and modifying the drive waveform in response to the error signature.

Abstract: A voltage translator circuit is disclosed herein that eliminates the need for two supply voltages to achieve voltage translation through the use of supplying a shifted voltage threshold. Effectively, this voltage translator circuit has very little supply current (Icc) after the device switches. Specifically, the voltage translator in accordance with the present invention includes a first and second inverter coupled in series between an input node and an output node. A third inverter connects between the output node and a fourth inverter. A first circuit portion that establishes the low-to-high switching point connects between the fourth inverter and the first inverter. A second circuit portion connects between the fourth and first inverter that will block the switching current from draining the voltage supply after the transition from low-to-high has occurred.

Abstract: A microelectromechanical device having a movable element with low mass inertia is disclosed herein. The movable element is held on a substrate such that the element is capable of rotating relative to the substrate; and the element has a mass inertia of 1.2×10?24 kg·m2 or less.

Abstract: A projection system, a spatial light modulator, and a method for forming a MEMS device is disclosed. The spatial light modulator can have two substrates bonded together with one of the substrates comprising a micromirror array. The two substrates can be bonded at the wafer level after depositing a getter material andlor solid or liquid lubricant on one or both of the wafers. The wafers can be bonded together hermetically if desired, and the pressure between the two substrates can be below atmosphere.