Abstract: A threshold correcting reference voltage generator in which a capacitor is charged from a first voltage source to a voltage above the desired corrected reference voltage by means of a charging transistor controlled by a clock pulse. A metering transistor has its drain and gate electrodes connected to the capacitor either directly or through a blocking transistor. The source of the metering transistor is connected to a second voltage source which has a value below the desired corrected reference voltage. The charging transistor is then turned off and the blocking transistor, if present, turns on. Charge flows from the source to the drain of the metering transistor, reducing the capacitor voltage until the metering transistor just turns off. At this point the capacitor voltage is higher than the second voltage source by the threshold voltage of the metering transistor.

Abstract: Minimal random disk write latency is achieved by limiting the number of logical address blocks that can be serviced by a disk to less that the actual number of physically addressable blocks of the system and having a disk controller dynamically map logical data blocks to physical disk blocks in such a fashion that each logical write can take place to any free location, where the free location can be chosen in any track of the current cylinder.

Abstract: A portable PC is provided with a mechanism for elevating and lowering a pointing device in the keyboard of the PC. The elevating and lowering mechanism elevates and lowers the pointing device in response to the opening and closing of the cover of the computer to provide a proper operating height to the pointing device when the cover is open while reducing the thickness of the PC with the cover closed.

Abstract: A power supply apparatus which stabilizes the output by feeding it back is provided which suppresses variations of the output for abrupt variations of the input. The power supply apparatus comprises output sensing means for sensing output current and output voltage, first output control means for controlling the output with the increment or decrement of the value obtained from said output sensing means, second output control means for controlling the output from an absolute value of the input voltage, and selection means for selecting either said first output control means or said second output control means.

Abstract: The liminance within the viewing angle of an LCD device is increased by using an optical film of transparent material. The film has a first surface having a wave structure including a plurality of isosceles triangle prisms arranged side-by-side, and a second surface having an optically rough structure for performing diffuse transmission. The film may also have a first surface having a structure including a plurality of quadrangular prisms arranged side-by-side, and a second surface having an optically rough structure for performing diffuse transmission.

Abstract: To prevent dielectric breakdown for a storage capacitor of a liquid crystal display element connected to a predetermined gate line in a liquid crystal display device.

Abstract: The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

Abstract: A packet switch (25.sub.1) contains input port circuits (310) and output port circuits (380) inter-connected through two parallel paths: a multi-slot central queue (350) and a low latency by-pass cross-point switching matrix (360). The central queue has one slot dedicated to each output port to store a message portion ("chunk") destined for only that output port with the remaining slots being shared for all the output ports and dynamically allocated thereamong, as the need arises. Only those chunks which are contending for the same output port are stored in the central queue; otherwise, these chunks are routed to the appropriate output ports through the cross-point switching matrix. Each receiver classifies its resident chunks (as critical or non-critical) based upon both the urgency with which that chunk must be transmitted to its destination output port and by the status of the central queue. A critical chunk, i.e.

Abstract: The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

Abstract: A parallel computer system is disclosed comprising a plurality of high level processors joined together using a cross-point or cross-bar switch. The system includes an adapter between each processor and the switch. Protocol processing to drive the switch, transfer pages and schedule transmissions between the processors is performed by the adapter. The protocol use the notion of typed or tagged buffer management that allows a client to bind the semantics of a message being sent or received. These semantics specify behaviors in the protocol when message packets depart or when they arrive.

Abstract: The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

Abstract: A new machine design minimizes latency between many high performance processors and a large amount of shared memory. Wire length, latency and skew are minimized by stacking edge connected modules (ECMs). The ECMs are characterized by signal input/output (I/O) pads on three edges, the two opposing inside connector edges and the third global connector edge. The ECMs support multiple processors per module, a plurality of basic storage modules (BSMs) per module, and portions of request and response switches per module. A plurality of processor ECMs and request switch ECMs are stacked in a first stacks and a plurality of BSM ECMs and response switch ECMs are stacked in a second stack. The two stacks are arranged adjacent one another with the request switch ECMs above or below the processor ECMs and the response switch ECMs below or above the BSM ECMs so that the response switch ECMs are adjacent the processor ECMs and the request ECMs are adjacent the BSM ECMs.

Abstract: A data processing I/O system including a main storage for storing data and data processing instructions arranged in software programs, and a channel subsystem having hardware for reporting conditions in the channel subsystem to the software. A special Channel Subsystem Call (CHSC) instruction is used to store event information from the channel subsystem into the main memory for use by the software such that new or restored resources such as a channel path, a channel path and partial control unit link address, or a channel path and full control unit link address, may be originally made accessible, or may be restored to the I/O system. A mechanism is also provided to inquire of a device how long it expects to not be accessible to give the device sufficient time to reset itself before it is varied offline, thus preventing a device from being isolated or "boxed" prematurely.

Abstract: A system for resolving structural ambiguities in syntactic analysis of natural language, which ambiguities are caused by prepositional phrase attachment, relative clause attachment, and other modifier-modifiee relationships in sentences. The system uses instances of dependency (modification relationship) structures extracted from a terminology dictionary as a knowledge base. Structural ambiguity is represented by indicating that a word in a sentence has several words as candidate modifiees. The system resolves such ambiguity by 1) first searching the knowledge base, which contains dependency information in the form of tree structures, for dependencies between the word and each of its possible modifiees, 2) then assigning an order of preference to these dependencies by means of a path search in the tree structures, and 3) finally selecting the most preferable dependency as the modifiee. The sentences can be analyzed by a parser and transformed into dependency structures by the system.

Abstract: A mechanism for establishing a logical relationship between a channel and a control unit, called a logical channel path, in a computer input/output system wherein a dynamic switch is provided between the channel and the control unit. The disclosed logical path mechanism provides for the sharing of the same physical path by one or more channels to one or more control units. The initialization procedure disclosed identifies each sharing channel to each control unit configured to that channel for identifying the physical path to that channel in an input/output system wherein a switch between the channels and the control units provides a multipoint topology.

Abstract: A two-level multiple bit error correction scheme includes at the first level a memory chip with a memory error detection capability that produces a chip error signal (CES) when it detects errors in the bits leaving that chip and at the second level an off-chip ECC facility which interprets generated syndrome bits and chip error signals in order to determine which bits are bad. There are two types of codes distinguished by the absence or presence of parity bits. The use of parity bits allows for the detection of single bit errors in data read from the chip. Therefore, the CES is active only for detected multiple bit errors. Chips not using parity bits are less expensive, but the CES must be active for both single bit and multiple bit errors.

Abstract: An improved resource management system for a network-based computer system is described. The computer system includes a plurality of processors interconnected by a network where some of the processors are user nodes and others are batch nodes. The management system includes a delivery system for receiving the requests from the user nodes and a separate scheduler system for scheduling which request Go process next and on which batch node.

Abstract: Adapters attach the bus or video display of a personal computer or workstation to a high performance parallel interface (HIPPI) channel of a host computer. The HIPPI channel operates at a burst rate of 100 megabytes (MB) per second. The adapter includes an electrical circuit interface to provide compatible signal levels between the HIPPI channel and the bus of the personal computer or workstation. The adapter attaching the bus includes a first-in, first-out (FIFO) buffer that receives data words from the HIPPI channel. Control logic monitors the status of the FIFO buffer and interlocks the operation of the personal computer or workstation bus with the HIPPI channel so that proper data transfer is performed by the FIFO buffer. The adapter attaching the video display includes a pair of buffers operating in a ping-pong fashion to allow data to be written while data is being read. The buffers can be addressed by the personal computer or workstation as if they were internal memory.

Abstract: A data mechanism having a random access memory (RAM) which has a plurality of groups of memory chips, each group being divisible into two equally sized chip sets. Each group of memory chips is addressed by a first address and each individual memory chip is addressed by a second address. The random access memory contains stored data. A cache, connected to the RAM, stores a portion of data stored in the RAM and is accessed by a cache address for separately reading requested data therefrom. The cache provides a cache miss signal when it does not contain the requested data. A CPU, connected to the cache and the RAM, receives the cache miss signal and provides responsive thereto, a starting address to the random access memory for starting a block transfer from the random access memory to the cache in two shots. The starting address includes the first address and the second address.

Abstract: A convertible cooling module, especially for use in conjunction with a wide range of computer systems ranging from workstations to massively parallel processors is employable with both air and water cooling systems. In particular, a cooling module is convertible from a heat sink modality to an air cooling modality, and finally to a liquid cooling modality in response to either increased performance demands or an increase in the number of processors or circuit components employed. The conversion may be carried out in the field and provides a flexible and less costly upgradeability path for computer customers.