Abstract: A single error correcting double error detecting (SEC/DED) error correcting code for a memory is used to correct one fixed error and one transitory error in a data word stored in the memory. The erroneous data word and syndrome generated therefrom by the error correcting code circuitry are saved while the memory location of the flawed word is checked to determine the location of the one fixed error using a ancillatory error correction technique. A syndrome is then generated for the word assuming only a single fixed error in the location determined using the ancillatory technique. Thereafter, the generated and saved syndromes are exclusive OR'd together to obtain another syndrome locating the position of the transitory error. With both errors located, the word is corrected by inverting the erroneous data bits.

Abstract: This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register with gate electrode structures that are interdigitated with the gate electrode structures of each last stage of a plurality of parallel shift registers to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order.

Abstract: An improved Field Effect Transistor (FET) with a very small effective channel length is made by using, a first ion implantation to produce the source and drain regions of the FET and a second very shallow ion implantation next to the source region to produce the effective short channel of the FET. The effective channel of the FET is implanted to only a small fraction of the depth of the source and drain. The use of implantations instead of diffusions in the described manner in combination with the use of the shallow effective channel in the FET provides superior control over the threshold voltage of the FET and increases the operating speed of the FET.

Abstract: A protection circuit is provided in which the output voltage is sensed and the output device is shut-off for protection when the output voltage falls below a predetermined trip voltage. The monolithic integrated circuit includes a voltage shifting circuit for transferring the output voltage to a biasing circuit which biases a switching circuit which turns the line driver off, when an overload or short circuit causes a voltage drop below a predetermined trip voltage. The protection circuit is disabled during start-up or signal rise time by splitting the input signal into two separate paths in which the signals have different delays. The shorter delay allowing the input signal to rise and to appear on the output line before the longer delay input signal rises enabling the protection circuit.

Abstract: A semiconductor chip mounted on a substrate by solder columns connecting one side of the chip to the substrate, is removed from the substrate by cooling the unconnected side of the chip to embrittle the solder columns and then twisting the chip with small angle rotational motion to shear the columns at their midpoints. A mechanism for cooling and rotating the chip makes use of the cooling substance to minimize the contact of the substrate with the cooling substance.

Abstract: This specification describes the testing of interconnections between modules mounted on a card and between the modules and the input and output terminals of the card. Each of the modules has an Exclusive-OR circuit which receives an input from each of the input pins of the module and has a single output which is taken off an output pin of the module. Also, each of the modules has a test input circuit for accessing all of the output pins of the module in parallel from a single input terminal. The test input circuits are used to apply a binary 0 followed by a binary 1 to all the outputs of all the modules. The Exclusive-OR circuits are used to monitor the response to those signals. By testing in this manner, all the connections between the modules and also between the modules and the card terminals can be checked for stuck ones and zeros.

Abstract: This specification describes apparatus for reading and decoding data encoded in terms of the spacing between adjacent code bars on a document. The apparatus contains reading means for producing an electrical pulse for each bar recorded on the document as the bar passes the reading element. A counter is used to measure the time between each two pulses and the resultant counts are stored in a memory in the order in which the pulses were produced by the reading means. A microprocessor then compares this stored data with microcoded data representative of properly coded digits. If there is a compare the stored data is shifted out of the memory and into a computer for use. However if there is a no-compare the microprocessor alters the data on the assumption that a particular type of error has occurred and again compares the modified data with the microcoded data. If this results in a compare the modified data is again read out and into the using computer.

Abstract: A programmable logic array (PLA) is provided with a plurality of storage registers. The PLA includes an AND matrix which generates inputs to an OR matrix which in turn selectively feeds output signals into the storage registers. At a selected time, a selected storage register provides the output signals of the PLA and/or feedback signals to the AND array so that sequential logic functions can be performed in the PLA. The plurality of storage registers are used to store various combinations of the OR matrix output signals. A decoder permits selection of one of the registers at a time to allow time discrimination among the various stored combinations of the OR matrix output signals for the purposes of feeding them out of the PLA and/or feeding them back into the AND matrix.

Abstract: This specification describes a programmable logic array (PLA) for performing logic functions on binary variables in a plurality of sequentially functioning arrays in which at least one of the arrays is conditionally powered when and only when the binary variables are supplied to the PLA in a logically useful combination.

Abstract: This specification deals with testing of a network of electrical interconnections between chips mounted on an insulative substrate of a module and between the chips and the input and output pins of the module. Each of the mounted chips contains masking circuits which can be activated to prevent controlling signals from the outputs of logic circuits on the chip from being transmitted off the chip and into the interconnection network. Also each of the chips contains emitter follower circuits that logically connect all the chip input terminals to a common output terminal of the chip. In testing the mask circuits are activated. Then potential levels are selectively applied to a plurality of test points in the interconnection network and differences in potential level between these test points and/or between the points and one or more of the common terminals are determined.

Abstract: This specification describes transferring a partial block of data with first and last words that are partial words from a processor and storing it in a memory protected by an error correcting code that requires the words to be stored in the memory as whole words. Prior to the initiation of the transferring and storage procedure, the memory is accessed and data words corresponding to the partial words in the partial block of data are fetched and placed in registers. Thereafter, during the transferring of the partial words, the fetched words are combined with the partial words to generate full words. Error correction check bits are added to these generated full words and the combination is stored into the memory.

Abstract: This specification describes an array logic chip that can be used to encipher and decipher binary data. The array logic chip contains a matrix of input and output lines with the input lines divided into groups that are each addressed by a different decoder. The digits of a block of data to be encoded are arranged in sets according to the position of the digits in the block and a different set of digits is fed into each of the decoders of the array logic chip. Substitution of new digits for the original digits in each set is accomplished in the matrix by configuration of connections between a group of input lines and output lines of the arrays and in the decoders by changing the configuration of the decoders so as to vary the input lines of the matrix selected by the input signals to the decoders. Transposition or changing of position of the digits in the block of data is accomplished in the selection of the output lines to which any given group of input lines is connected.

Abstract: This specification describes image rotation hardware for allowing the displaying of an image stored in digital form in other than its originally stored orientation. In this hardware a word-organized image buffer stores a digital representation of a full image with each picture element (pel) of the full image being represented by a bit within the buffer. The buffer is divided into a plurality of square sections each storing a portion or subimage of the full image. Each section is n.times.n bits in size where n is the number of bits in a word stored in the buffer. The contents of each square section of the buffer can be transferred into an n.times.n storage array with first word organization, and then transferred back into the buffer with second word organization such that the subimage stored by the square section is rotated through 90.degree..

Abstract: This specification deals with the stopping, positioning, orienting and redirecting a semiconductor wafer being transported along a track on an air film or bed of air. The stopping mechanism is an air jet located in a groove in the track, wafers passing over this air jet on an air film are sensed by a pneumatic sensor that turns on the air jet to set up an air stream under the transporting surface of the air film. This air stream sucks the fluid in the air film along with it in the groove causing a vacuum in the bed in the area of the nozzle of the air jet. The wafers are then stopped by the suction of the vacuum. Positioning, orienting and redirecting is done using the air jet and pneumatic sensor in combination with special air jet arrangements and operations.

Abstract: This specification describes a charge-transfer device transversal filter chip in which an input signal is fed in parallel into a number of channels the outputs of which are summed together to provide the desired transversal filter transfer function. Each channel contains an analog shift register, a signal splitter and a polarity selector. The shift registers are of unequal length to provide a different delay thru each channel. The signal splitter provides a plurality of signal paths thru each channel while the polarity selector determines whether a given path in a given channel is added or subtracted in the summation to determine the gain of the given channel in the summation.

Abstract: This specification relates to performance of partial store operation in a hierarchical memory system which has a buffer store interposed between a processor interrogating the memory system and the main memory of the memory system. Such a partial store operation can be performed on a word of data in the main memory using the buffer store copy of that word of data. The copy of the word of data is read out of the buffer store into a register where it is modified to form a new word by replacing one or more but not all of the bytes in the word of data with bytes supplied by the processor. The new word is then placed in the main memory by performing a full store operation. The problem with performing a partial store operation in this manner is that the copy of the word of data in the buffer store may not be up-to-date. A technique is provided to eliminate the possibility of this old data being rewritten back into the main memory.

Abstract: An array of optically sensitive devices senses printed matter with each device in the array producing an output signal representing a single black or white element in a multi-element picture being sensed by the whole array. These output signals are fed into an analog charge transfer shift register and passed serially in a fixed sequence through an output stage of the shift register. As the signal from each device passes through this output stage the device becomes what is hereafter referred to as the device of interest and the signal produced by it is analyzed to determine whether it is a black or white element. Other output stages simultaneously sense data from devices located around the device of interest to define a subarray within the original detected array while the last of these output stages is fed to a peak comparator to sense the brightest and darkest matter detected in the recent past by any element of the array.

Abstract: This monochromator is made up of a number of discrete narrow band interference filters mounted on a drum which rotates with respect to a light beam so that as the light beam passes through each of the filter the angle of incidence of the light beam changes with respect to the filter. Each of the filters is for a different normal wavelength of peak transmission so that spectral analysis of the light source can be obtained.

Abstract: This is a multi level or hierarchial memory system for a multi processing system in which two or more processing units access the memory system. This memory system has two types of memory units on each level with the exception of the lowest level. One of the types of units is called the data store and is for storing all the data at any given level of the memory. The other type of unit is called the copy back store and is for storing all the changes that have been made in data at that level either by addition or modification. The next to lowest level of the hierarchy the data store and copy back stores are embodied in magnetic disc units and the lowest level of the hierarchy the data stores are embodied in a tape unit with multiple input stations. The disc and tape units are all serially strung together on two independent accessing loops which access the tape unit through a different one of the input stations of the tape unit.

Abstract: The transportation of semiconductor wafers along a track on an air film. The supporting air film is controlled by the track configuration and fluid relationships to eliminate the need of a wafer guide on restraint to keep the wafers on the track.