Abstract: This is a hierarchial memory system for a multi-processing system which has two or more processing units accessing the memory system. The memory system has two different types of memory units on each level. One of the types of units is called the data store (DS) and contains all the data at that level of the memory. The other type of unit is called the copy back data store (CBDS) and contains all the changes that have been made which changes data either by addition or modification and that are to be copied back to the next lower level of the memory hierarchy. The data store and the copy back data store in each level are on two different power systems and transfers of the changes to the next lower level are done in the order in which the change entered in the copy back store with the oldest entry being the first to be copied back. Each copy back data store has a capacity which is only a small portion of the data capable of being stored in the corresponding data store.

Abstract: A virtual memory system is described in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory location called a real address. To avoid the necessity of translating the same address over and over again, a table called the Directory Look Aside Table (DLAT) retains current virtual to real address translations for use where particular virtual addresses are requested more than once. A counter is associated with the DLAT. Each time a translation is stored in the DLAT the present count in the counter is stored along side the translation. Each time the DLAT is invalidated the counter is stepped so that with each invalidation a new number is stored in the DLAT with the next translation. When a translation is read out of the DLAT the number stored with the translation is compared with the present number in the counter. If they do not match a No Compare signal is provided.

Abstract: This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations:P.sub.8.sup.a = i.sub.8.sup.a .sym.i.sub.8.sup.b .sym.i.sub.6.sup.b .sym.i.sub.1.sup.b .sym.i.sub.3.sup.c .sym.i.sub.2.sup.cP.sub.8.sup.b = i.sub.8.sup.a .sym.i.sub.6.sup.a .sym.i.sub.3.sup.a .sym.i.sub.5.sup.b .sym.i.sub.8.sup.c .sym.i.sub.4.sup.cwhere i.sub.8.sup.a, i.sub.8.sup.b and i.sub.8.sup.c are the three information bits in the set associated with the parity bits P.sub.8.sup.a and P.sub.8.sup.b while the other information bits are from the seven sets of the sequence preceding the set associated with the parity bits.

Abstract: This specification describes a set of arrays for performing logic function in various subsets of the original set. The array structure is characterized by a plurality of arrays joined together with a bidirectional bussing system. This bussing system comprises addressing lines of the arrays joined together by switching circuitry used to regroup the set into subsets as necessary to perform the logic functions.

Abstract: This specification describes a decoder for a programmable logic array (PLA) having opposite ends of input lines of the array connected to outputs of different decoders. Previously two-bit decoders were arranged on opposite sides of the array to generate input variables from two sets of two different input signals each and feed those input variables to four input lines. Here, instead of using two-bit decoders, four one-bit decoders are positioned on each side. The outputs of these one-bit decoders are programmable to change the connections between them and the input lines of the array. The arrangement permits the decoders to perform one-bit, two-bit decoding on signals on the same side of the input lines, to do two-bit decoding on signals on opposite sides of the array and in combination with other sets of decoders to do three and four-bit decoding of input signals.

Abstract: This specification describes a decoder for use in a programmable logic array (PLA) of the type having opposite ends of input lines of the array connected to outputs of different decoders. Instead of using the outputs of two two-bit decoders to drive four input lines, as was previously done, four one-bit decoders are used to drive the four input lines. This arrangement permits the one-bit decoders with minor modifications to be used to perform four one-bit decodes of four input signals, two two-bit decodes on two sets of two input signals on either side of the array and one two-bit decode on two input signals that are on opposite sides of the array.

Abstract: This specification describes an associative memory cell capable of performing logic functions. The cell comprises two transistors with their collectors connected to an output line; with their emitters either left floating or connected to an input line carrying either true or complement of one variable; and with their bases either connected to an input line carrying the true or complement of a second variable or to the output line which is maintained at a fixed potential. This permits the performing of sixteen different logic functions of the two input variables by the cell.

Abstract: Two separate address lines are provided for each storage line of local storage. One address line is connected to a first group of bytes and the second address line is connected to the remaining bytes with each storage line containing the same addressing connection. Control circuits are provided for selecting any two address lines where the combination of the two provides access to both byte groups.

Abstract: This hierarchical memory system has two memory units on each level. One of the units called the data store contains all the data at that level of the memory. The other unit called the copy back store contains all the changes that have been made in that data either by addition or modification. While the data store is interfaced with the next higher level in the hierarchical memory system or with the processing units for the data processing system, the second or copy back store can transfer the changes made in the data into the next lower level in the memory hierarchy system if the copy back store is free and the data store in the next lower level is not involved in transferring data up the hierarchy. The data store and the copy back data store in each level are on two different power systems and transfers of the changes to the next lower level are done in the order in which the change entered in the copy back store with the oldest entry being the first to be copied back.

Abstract: This specification describes an apparatus for determining if more than one of n lines are up at a given time. The apparatus includes means for encoding the n lines into m lines where n = 2.sup.m. Two encoding signals are generated; one, X.sub.0 X.sub.1 . . . X.sub.m, complement of the other, Z.sub.0 Z.sub.1 . . . Z.sub.m. These two signals are Ex OR'd in accordance with the formula (X.sub.0 Z.sub.0) .sup.. (X.sub.1 Z.sub.1) . . . (X.sub.m Z.sub.m). If more than one line is up, the resultant of the Ex OR operation is one. Otherwise the resultant is zero.

Abstract: This specification describes an associative memory cell capable of performing logic functions. The cell comprises two transistors with their collectors connected to an output line and their emitters connected to an input line carrying either the true or complement of one variable. The bases of the two transistors can each be selectively connected to either the true and complement of a second variable or fixed at one of two reference or logic levels to permit the performing of sixteen different logic functions of the two input variables by the cell.

Abstract: This specification describes means that permit the variation of circuits, particularly latch circuits, used in programmable logic array chips (PLAs). The latch circuits are changeable to enable the selection of one of three different latch configurations to be used or in combination on the same PLA chip. The differences in the circuit configurations of the different types of latches occur only in metallization pattern of the chip so that chips with different latch configurations can be manufactured with a minimum of different processing steps.

Abstract: This specification describes a differential sense amplifier serving balanced sense lines. An imbalance in bias potential on the sense lines holds the sense amplifier in an insensitive state until just before data is to be read on the sense lines. Then a shunting device connected across the sense lines and across the inputs to the differential amplifier is activated to reduce the imbalance and thereby sensitize the differential amplifier. This shunting device is controlled by a feedback path that senses the biasing condition and shuts off the shunting device when the amplifier is in condition to perform the Read cycle.

Abstract: This specification describes arrays for performing logic functions. In these arrays, input variables can be fed to either or both ends of input lines. When input variables are fed to both ends of a line, the line is broken to separate logic performed on the variables fed to one end from the logic performed on the variables fed to the other end.The arrays are compounded. Two arrays are arranged on opposite sides of a third array and the output signals from the two arrays function as input variables to the third array. Input lines in the third array can also be broken to separate array logic functions performed in the third array on variables fed to the opposite ends of such lines.

Abstract: This specification describes a programmable logic array (PLA) in which the readout table or OR array for the PLA is broken into two segments and the segments placed on opposite sides of the search table or AND array for the PLA. The output lines for the AND array can then be split so that outputs on one segment of those lines are fed to the OR array on one side and outputs on the other portion of those lines are fed to the OR array on the opposite side. Likewise the output lines in the OR arrays can be broken so that different functions can be fed out to opposite sides of the OR arrays. It is also possible to break input lines in both the OR and AND arrays to isolate functions from one another.

Abstract: This specification describes an associative memory decoder for a memory system in which the units in the memory system are reconfigurable both in size and in number. The decoder is designed to take an address for that memory system and address memory space in the memory system irrespective of the amount of storage in the system so that the decoder has to change as memory capacity is added or subtracted from the memory system.

Abstract: This specification describes arrays for performing logic functions which include circuitry for testing the arrays to see if the arrays will perform the logic functions that they were designed to perform. This circuitry eliminates the need for storing information as to logic functions performed by any particular array and allows a uniform testing sequence to be used in testing all the arrays.

Abstract: This specification describes an orderly arrangement of input and output lines for a programmable logic array chip (PLA). In the arrangement, a plurality of parallel current conducting lines called rails are positioned on the chip along side the arrays of the PLA. The inputs and outputs of the arrays are selectively connected to individual rails so that the rails carry the input signals to the arrays from off the chip and take output signals of the arrays off the chip and to inputs of the arrays. The rails are selectively segmented so that each segment of a rail may be used as a path for an input and/or output signal without interfering with signals on other segments of the same rail.