Patents Represented by Attorney, Agent or Law Firm James E. Parsons
  • Patent number: 7587487
    Abstract: A technique to load balance network packet traffic using content switching is provided. Packets are routed to a particular server or otherwise processed based on the XML-related content identified in a header or body of the packet. Rules can be defined that specify an action to undertake with regards to the packet if certain pieces of XML-related content are identified therein. These actions can include forwarding of the packet to a particular server or servers that best process the transaction associated with the packet.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: September 8, 2009
    Assignee: Foundry Networks, Inc.
    Inventor: Anilkumar Gunturu
  • Patent number: 7356030
    Abstract: A switching fabric having cross points that process multiple stripes of serial data. Each cross point includes a plurality of port slices and ports. Each port includes a plurality of FIFOs, a FIFO read arbitrator, a multiplexer, a dispatcher, and an accumulator. In one embodiment, each cross point has eight ports and eight port slices. A method for processing a stripe of data at a cross point at one port slice includes storing data received from other port slices in a plurality of FIFOs and arbitrating the reading of the stored data. A step of writing data received from a port at the one port slice to an appropriate FIFO in a different port slice is also included. In one embodiment, a method for processing data in port slice based on wide cell encoding and an external flow control command is provided.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: April 8, 2008
    Assignee: Foundry Networks, Inc.
    Inventors: Andrew Chang, Ronak Patel, Ming G. Wong
  • Patent number: 7313714
    Abstract: A system and method for dynamically managing a plurality of power supplies for a computer system has a plurality of first circuits, each of the first circuits responsive to an electrical condition of each of the plurality of power sources. A second circuit is coupled to the plurality of first circuits, and is responsive to the plurality of first circuits. The second circuit identifies a state associated with any one of the plurality of power sources. A third circuit is coupled and responsive to the second circuit. The third circuit communicates the states of the plurality of power source to a user.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: December 25, 2007
    Assignee: Foundry Networks, Inc.
    Inventors: Charles A. Helfinstine, Chang-Pen Tai
  • Patent number: 7238104
    Abstract: A vent for a computer enclosure is envisioned. The vent system has a fan, operable to draw a flow of air from within the enclosure and direct it out through an outlet vent disposed in a wall of the enclosure. The outlet vent is made of an outlet path. The outlet path is defined by a first and a second side member. The first and second side members are attached to the enclosure and form an environmental seal. The outlet vent also has an outlet face oriented at a first angle relative to the wall. A plurality of slats are rotatably coupled to the outlet face. The plurality of slats maintain a first position when the fan is not operating. When the fan goes into an operational mode and produces an airflow, the plurality of slats swing radially outward to a second position. The plurality of slats return to the first position when the airflow is not present. The angle of the slats in the first position is nearer to parallel to the first angle than when in the second position.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: July 3, 2007
    Assignee: Foundry Networks, Inc.
    Inventors: Michael D. Greenslade, A. Fred Hendrix, Francisco Martinez-Ponce
  • Patent number: 7236490
    Abstract: A backplane interface adapter for a high-performance network switch. The backplane interface adapter receives narrow input cells carrying packets of data and outputs wide striped cells to a switching fabric. One traffic processing path through the backplane interface adapter includes deserializer receivers, a traffic sorter, wide cell generators, stripe send queues, a backplane transmit arbitrator, and serializer transmitters. Another traffic processing path through the backplane interface adapter includes deserialize receivers, a stripe interface, stripe receive synchronization queues, a controller, wide/narrow cell translator, destination queues, and serializer transmitters. An encoding scheme for packets of data carried in wide striped cells is provided.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: June 26, 2007
    Assignee: Foundry Networks, Inc.
    Inventors: Andrew Chang, Ronak Patel, Ming G Wong
  • Patent number: 7206283
    Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: April 17, 2007
    Assignee: Foundry Networks, Inc.
    Inventors: Andrew Chang, Ronak Patel, Ming G Wong
  • Patent number: 7035101
    Abstract: A power supply is contained substantially within an enclosure of length, L. A first end of the enclosure has a first end wall containing an air intake port, with a second end of the enclosure having a second end wall containing an air exhaust port. An exterior wall surrounding the power supply is coupled to the first and second end walls so that substantially all air entering the power supply does so through the air intake port and all air leaving the power supply does so through the air exhaust port. The enclosure contains an airflow generator for inducing an air flow within the enclosure from the air intake port to the air exhaust port, located at least a distance L/5 from the air intake port and air exhaust port.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: April 25, 2006
    Inventors: A. Fred Hendrix, Chang-Pen Tai
  • Patent number: 6830955
    Abstract: A semiconductor package and method for manufacturing the same is disclosed. The semiconductor package comprises a semiconductor chip, a circuit board, an electrical connection means, an encapsulation material and a plurality of conductive balls. The semiconductor chip has a first surface and a second surface. A plurality of input and output pads are formed on one of the first and second surfaces. The circuit board comprises a thin film having a first surface and a second surface and being provided with a center hole in which the semiconductor chip is positioned, a plurality of circuit patterns being formed on the first surface of the thin film and including a plurality of bond fingers and ball lands, and a cover coat covering the circuit board except for the bond fingers and the ball lands. The electric connection means electrically connects the input and output pads of the semiconductor chip with the bond fingers of the circuit board.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: December 14, 2004
    Assignee: Amkor Technology, Inc.
    Inventors: WonSun Shin, DoSung Chun, SeonGoo Lee, SangHo Lee, Vincent DiCaprio
  • Patent number: 6815353
    Abstract: A method for improved dielectric polish control adjacent to device areas is described. This is particularly important for bipolar structures, although the method may be used for MOS structures as well. The method includes using highly selective methods for removing oxide layers and polish stop layers in a multi-layer film stack, providing an oxide edge step height that is substantially uniform regardless of the size of the adjacent device area. In one embodiment, the multi-film stack includes a first oxide layer, first nitride layer, second oxide layer, and second nitride layer. The multi-film stack is deposited on a substrate. Trenches are then etched through the multi-film stack and into corresponding regions of the substrate. A passivation oxidation layer is grown on the etched trench surfaces. The trenches are filled with oxide for isolating active device regions from one another. A first STI polish is performed, polishing the trench oxide to the level of the second nitride layer, which is then removed.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: November 9, 2004
    Assignee: Micrel, Incorporated
    Inventors: Ronald L. Schlupp, Linda Koyama
  • Patent number: 6806558
    Abstract: A combination edge- and broadside-coupled transmission line element formed in an integrated circuit chip, using semiconductor processes, in a stack of metal layers separated by dielectric layers. Each of the metal layers includes a number of transmission lines. Interconnects between the transmission lines are formed at predetermined locations, each interconnect electrically connecting together a group of the transmission lines to form a conductor. The efficiency of the coupling between the lines in the different conductor is increased by positioning the lines such that both edge and broadside-coupling is realized. For example, at least one of the transmission lines in one of the conductors is positioned either above or below a transmission line in the other conductor to achieve broadside-coupling and laterally adjacent to another transmission line in the other conductor to achieve edge-coupling.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: October 19, 2004
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Thomas R. Apel
  • Patent number: 6803254
    Abstract: A wire bonding method for electrically interconnecting stacked semiconductor chips is disclosed. A substrate (e.g., printed circuit board or metal leadframe) is provided. Metal circuit patterns are provided outside of a chip mounting region of the substrate, and metal transfer patterns are provided proximate to the chip mounting region. Stacked semiconductor are disposed in the chip mounting region. Conductive wires are bonded between respective pads of one stacked chip and respective transfer patterns, and other conductive wires are bonded between respective pads of the other stacked chip and the same respective transfer patterns, thereby electrically connecting respective pads of the two chips through a pair of bond wires and an intermediate transfer pattern. The transfer patterns are separate from circuit patterns of the substrate. At least one of the first and second chips is electrically connected to some of the circuit patterns for external connection.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: October 12, 2004
    Assignee: Amkor Technology, Inc.
    Inventors: Young Kuk Park, Byung Joon Han, Jae Dong Kim
  • Patent number: 6798049
    Abstract: A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin layer and a circuit pattern. The resin layer is provided with an opening at its center portion. The circuit pattern is formed on at least one of upper and lower surfaces of the resin layer and includes one or more bond fingers and ball lands exposed to the outside. The semiconductor chips have a plurality of input/output pads on an active surface thereof. The semiconductor chips are stacked at a position of the opening of the circuit board, with at least one of the chips being within the opening. Alternatively, both chips are in the opening. The electric connection means connects the input/output pads of the semiconductor chips to the bond fingers of the circuit board.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: September 28, 2004
    Assignee: Amkor Technology Inc.
    Inventors: Won Sun Shin, Do Sung Chun, Seon Goo Lee, Il Kwon Shim, Vincent DiCaprio
  • Patent number: 6791166
    Abstract: A die package is formed, which allows additional electrical connections to the die by using internal leads or traces from a lead frame. The internal leads are exposed through an upper or lower surface of the package, thereby allowing an additional die package to be stacked and electrically connected to the underlying die or additional inputs/outputs to underlying external circuitry, such as a printed circuit board.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: September 14, 2004
    Assignee: Amkor Technology, Inc.
    Inventor: Donald Craig Foster
  • Patent number: 6787826
    Abstract: A high electron mobility transistor is constructed with a substrate, a lattice-matching buffer layer formed on the substrate, and a heavily doped p-type barrier layer formed on the buffer layer. A spacer layer is formed on the barrier layer, and a channel layer is formed on the spacer layer. The channel layer may be of uniform composition, or may be made from two or more sublayers. A Schottky layer is formed over the channel layer, and source and drain contacts are formed on the Schottky layer. The substrate may be gallium arsenide, indium phosphide, or other suitable material, and the various semiconductor layers formed over the substrate contain indium. The transistor's transition frequency of the transistor is above 200 GHz.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: September 7, 2004
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Hua Quen Tserng, Edward A. Beam, III, Ming-Yih Kao
  • Patent number: 6785191
    Abstract: A data word is used to represent the total amount of time duration or predefined events a device has experienced during its lifetime. The data word is incremented count by count while the device is powered on and each updated data word is backed up to a non-volatile memory. A two-version redundancy scheme is employed to ensure failsafe backup and restoration of the data word. At any time at least one valid version of the data word exists in the non-volatile memory. In another aspect, a partitioned memory configuration is implemented to backup the data word and its associated error correction code to the non-volatile memory. In this way the non-volatile memory is able to store a range of counts whose maximum number far exceeds the memory's endurance limit.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: August 31, 2004
    Assignee: Micrel, Inc.
    Inventor: Peter Chambers
  • Patent number: 6778681
    Abstract: Systems and methods for non-intrusive analysis and display of internal features of wooden objects are provided. In embodiments of the system, a log is passed through a CT scanner in one continuous motion. One or more x-ray sources revolve around the log generating x-ray beams that traverse contiguous cross-sections of the log. An array of x-ray detectors detects x-rays that traverse the log for variations in the attenuation of rays. The detected attenuation is converted into spiral scan data that corresponds to projections in different contiguous cross-sections traversed by the x-rays. An image processor reconstructs spiral scan data into two dimensional cross-sectional images of the log by processing and formatting scan data using a planar reconstruction technique. The system renders three-dimensional views based on two-dimensional images.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: August 17, 2004
    Assignee: InVision Technologies, Inc.
    Inventors: Walter I. Garms, James M. Carver
  • Patent number: 6771053
    Abstract: A digital potentiometer, configurable and programmable using nonvolatile memory is disclosed. A unity-gain configured, rail-to-rail operational amplifier, used as voltage follower of buffer, can be inserted, by programming, between an internal wiper terminal and an output terminal of the digital potentiometer. This way, in certain applications, it is possible to take advantage of the low output resistance given by an analog buffer. The operational amplifier can be shutdown and bypassed by a switching device to provide a circuit behavior similar to a digital potentiometer without an output buffer. Using a dual-writing circuitry, first the complemented data, then the data itself, are written in the nonvolatile memory, improving the reliability. A Gray-code counter having a single bit changed at one time and no decode glitch is present. A make-before-break circuitry gives a short overlap conduction time for any adjacent pair of switches; one being turned-off while the other is turned-on.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: August 3, 2004
    Assignee: Catalyst Semiconductor, Inc.
    Inventors: Cornel D. Stanescu, Adrian M. Tache, Horia Profeta, Radu H. Iacob, Adam P. Cosmin
  • Patent number: 6762078
    Abstract: Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: July 13, 2004
    Assignee: Amkor Technology, Inc.
    Inventors: WonSun Shin, DoSung Chun, SangHo Lee, SeonGoo Lee, Vincent DiCaprio
  • Patent number: 6762647
    Abstract: A peak detector detects an amplifier output overvoltage condition if the amplifier drives a mismatched load impedance. In response to the detected overvoltage condition, a clamping transistor lowers a reference DC bias voltage supplied by a bias circuit to the amplifier. The lowered reference DC bias voltage lowers amplifier gain and output power, thus protecting the amplifier.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: July 13, 2004
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Thomas R. Apel
  • Patent number: D494999
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: August 24, 2004
    Assignee: UltraCard, Inc.
    Inventor: Bert D. Cook, Jr.