Abstract: Disclosed herein are semiconductor packages and stacks thereof. An example package includes an insulative substrate having a first surface, first apertures, a second aperture, and circuit traces on the first surface. A first portion of each circuit trace overlies a first aperture and an end of the circuit trace is near the second aperture. A solder ball is in each first aperture, fused to the overlying circuit trace. A semiconductor die is in the second aperture and is electrically connected to the ends of the traces. A third aperture may extend through the first portion of each circuit trace. A second package can be stacked on a first package. Solder balls of the second package each fuse with an underlying solder ball of the first package through a third aperture of the first package. The dies of the stacked packages may be positioned for optical communication with each other.

Abstract: A method of making a PCB having an integral heat spreader and/or central ground plane includes forming one or more first openings in a first layer of a metal at selected locations and filling the. openings with an electrically insulating material. The first sheet is laminated between second and third layers of a metal interleaved with first and second layers of a dielectric material. At least one second opening is formed through the insulating material in one of the first openings, and at least one third opening is formed in the laminate at a position displaced from the first openings. The upper and lower layers of metal are electrically connected to each other through the at least one second and third openings to define “vias” through the laminate. The vias comprise “clearance vias” from which the first metal sheet is electrically isolated, and “thermal vias” to which the first metal sheet is electrically connected.

Abstract: An apparatus for mounting an electronic device on a substrate without soldering is disclosed. The apparatus includes a body and a plurality of cantilever beams extending from the body. The apparatus is mounted on the substrate. The electronic device is placed within the apparatus. In one embodiment, the cantilever beams press against the electronic device. In another embodiment, the cantilever beams engage the substrate. The apparatus presses an array of electrical contacts of the electronic device (e.g., interconnection balls) against corresponding metal pads of the substrate, thereby forming an electrical connection.

Abstract: Semiconductor packages and other electronic assemblies having an active heat sink are disclosed, along with methods of making the same. The active heat sink includes a cavity partially filled with a heat activated liquid. Heat generated during operation of a chip boils the heat activated liquid. The vapor condenses on an inner surface of the active heat sink and transfers heat to an outer, possibly finned, surface exposed to ambient to dissipate heat. In some embodiments, the active heat sink may be a closed vessel mounted on the chip. In some embodiments, the vessel of the active heat sink is formed from a die pad of a leadframe substrate. The die pad includes a recess that forms the active heat sink cavity when bonded to the back surface of the chip. The heat activated liquid directly contacts the back surface of the chip in these embodiments.

Abstract: A stackable package for an integrated circuit (e.g., a flip chip) is disclosed. The package includes a molded plastic package body having a first side, an opposite second side, and side surfaces extending vertically between the first and second sides. A plurality of leads extend from the package body. Each lead has a first portion embedded in the package body, a second portion extending vertically adjacent to a peripheral side surface of the package body, and a third portion adjacent to and extending over first side of package body. A surface of embedded first portion of the leads is exposed at the second side of the package body. The package may be vertically stacked on another package and electrically connected thereto. Keys extending from the package body of the first package engage keyholes of the other package. A heat sink is horizontally disposed between the packages. The heat sink has a rectangular body and radiating fins.

Abstract: A leadframe and molded semiconductor package made using the leadframe are disclosed. The leadframe includes leads extending from a dam bar toward a central chip mounting region. A pseudo tie bar extends diagonally from three of the four corners of the dam bar toward the chip mounting region. A resin introduction slot is at the remaining corner of the dam bar. The resin introduction slot is wider than a space between adjacent leads. The leads adjacent to the resin introduction slot increase in width as they extend from the dam bar toward the chip mounting region. The leadframe is used to form a semiconductor package having a package body formed of a molded resin. The leadframe design minimizes voids and damage caused by the molding process.

Abstract: A method of making a package for an integrated circuit device having an optical cell is disclosed. The package includes a base of molded encapsulant material. A metal leadframe is embedded in the plastic base at the upper surface of the base. Encapsulant material covers the lower and side surfaces of the die pad and the leads of the leadframe, but does not cover the upper surfaces of the die pad and leads. An optical integrated circuit device is attached to the exposed surface of the die pad. An adhesive bead is applied around the optical device on the exposed upper surface of the leads. An optically clear cover is placed on the adhesive bead. When hardened, the bead supports the cover above the optical device.

Abstract: Embodiments of integrated circuit packages for housing a plurality of integrated circuits are disclosed, along with methods of making the packages. One integrated circuit package comprises a substrate having a first surface having first metallizations thereon, an opposite second surface, and a plurality of apertures between the first and second surfaces. A first integrated circuit having a first surface with first bond pads thereon and an opposite second surface is mounted on the second surface of the substrate so that the first bond pads are superimposed with an aperture. Each first bond pad is electrically connected by a first bond wire extending through the superimposing aperture to a first metallization. A second integrated circuit having a first surface with conductive second bond pads thereon is mounted on the second surface of the first integrated circuit.

Abstract: A plasma sputtering system that may be used to deposit a film on a substrate such as an optical disk is disclosed. In one embodiment, the sputtering system includes a main vacuum chamber. A plurality of sputtering chambers and a load lock chamber are connected to the main vacuum chamber. An assembly of a horizontal unprocessed substrate, an inner mask, and an outer mask are pressed onto a substrate transport tray that is positioned in the load lock. The tray supports the substrate and the masks throughout the processing of the substrate. A vertical lift lowers the tray from the load lock onto a carousel. The carousel transports the tray, substrate and masks to the sputtering chambers and then back to the load lock for unloading. Other lifts raise the tray, processed substrate, and masks from the carousel to the sputtering chambers. The tray is selectively pressed against the lower access aperture of the load lock and sputtering chambers so as to isolated them from the main chamber.

Abstract: A novel, moisture-resistant integrated circuit chip package is disclosed. In one embodiment, the integrated circuit chip package includes a substrate having a chip side and a backside. A first conductive layer is formed on the chip side of the substrate, and has a pattern forming conductive traces. A first soldermask layer is formed on the chip side of the substrate. The first soldermask layer directly contacts the first conductive layer. The first soldermask layer has at least one opening formed therein. A first contact layer is formed over the first conductive layer in the opening of the first. soldermask layer. A second conductive layer is formed on the backside of the substrate. A second soldermask layer is formed on the back side of the substrate and has at least one opening formed therein. A second contact layer overlies the second conductive layer in the opening of the second soldermask layer.

Abstract: A plasma sputtering system is described. A substrate handling system thereof places an unprocessed substrate (e.g., an optical disk), an inner mask, and an outer mask onto a tray in a loadlock of the sputtering system, and then seals the access opening to the loadlock. The substrate and the masks are moved on the tray to a sputtering chamber where the substrate is sputter coated. The substrate handing system removes the processec substrate and accompanying inner and outer masks from the tray in the loadlock to an external substrate change station, where the processed substrate is removed from the masks, which are still gripped by the substrate handling system. Another unprocessed disk is placed on the inner mask and within the outer mask, and the sequence repeats. The substrate handling system only contacts the masks on surfaces thereof that are not subjected to direct sputter deposition.

Abstract: The invention provides a manufacturing process for making chip-size semi-conductor packages (“CSPs”) at the wafer-level without the added size, cost, and complexity of substrates in the packages or the need to overmold them with plastic. One embodiment of the method includes the provision of a semiconductor wafer with opposite top and bottom surfaces and a plurality of dies integrally defined therein. Each die has an electronic device formed in a top surface thereof, and one or more electrically conductive vias extending therethrough that electrically connect the electronic device to the bottom surface of the die. The openings for the vias are formed ablatively with a laser and plated through with a conductive material. In a BGA form of the CSP, the vias connects the electronic device to lands on the bottom surface of the die. The lands may each have a bump of a conductive metal, e.g., solder, attached to it that functions as an input-output terminal of the CSP.

Abstract: A module of electrically interconnected integrated circuit packages and methods of making the module are disclosed. The module includes at least first and second integrated circuit packages, each of which are comprised of a package body formed of an encapsulant material. A plurality of leads extend from the package bodies of the first and second packages. The leads are bent into a C-shape. Keys and keyholes in the package bodies allow the packages to be stacked one on top of the other. One or more leads of the first package are electrically connected to one or more leads of the second package through an interposer that is positioned between the first and second packages. The interposer includes conductive paths that enable the electrical connection of leads of the first and second packages in cases where the leads to be interconnected are displaced from one and other.

Abstract: A plasma sputtering system is disclosed, along with methods of sputtering and methods of arranging an array of magnets disposed within the sputtering system. An embodiment of the sputtering system includes a vacuum chamber. A rotating magnetron is disposed in the vacuum chamber. A target is positioned between the magnetron and a substrate upon which material from the target is to be deposited. The magnetron includes an array of pairs of oppositely poled permanent magnets. A closed loop magnetic path extends between the pairs of oppositely poled magnets of the array. The magnetic path includes an inturn region proximate to an axis of rotation of the magnetron and at least two (e.g., five) indent regions.

Abstract: A method and apparatus for reinforcing the solder connections between a semiconductor device and a substrate includes the provision of a rigid frame having a central opening through it, a planar top surface, a bottom surface opposite and parallel to the top surface, and a thickness between the two surfaces to equal to the height of the solder connections. The top surface of the frame is attached to the bottom surface of the semiconductor device at the peripheral edges thereof and outside of a plurality of input/output terminals thereon. The bottom surface of the frame is attached to the top surface of the substrate. The frame reinforces the solder connections between a C4-mounted semiconductor die or a C5-mounted semiconductor package and a substrate against the stresses acting on the connections with bending of the PCB.

Abstract: A printer and components of the printer are described, along with methods of adjusting and using the printer. The printer includes a carriage that supports at least one printhead. The at least one printhead ejects ink onto a print media that is fed though a space between the printhead and a platen as the carriage moves laterally along slider rods supported by a beam. The space between the at least one printhead and platen is adjusted along the length of the printing path by applying a bending force to the underside of the beam that raises or lowers the beam relative to the platen at selected points. The adjustment is effected by one or more adjustment assemblies that abut the lower surface of the beam. In one embodiment, the first adjustment is an acorn nut and the second adjustment a differential screw that is engaged with the acorn nut.

Abstract: A semiconductor package and a method of making the package are disclosed. The package includes a semiconductor chip having first surface with a conductive pad thereon. A first end of a bond wire is connected to each of the pads. Encapsulant covers the fist surface of the chip, the pads, and the bond wires, and forms side surfaces of the package. A second end of the bond wires is exposed at a side surface of the package. Making the package includes providing a wafer including a plurality of semiconductor chip units. Each chip unit has a plurality of conductive pads at a first surface of the wafer. A bond wire is electrically connected between each pad of each semiconductor chip unit and a pad of at least one adjacent semiconductor chip unit of the wafer. An encapsulant is applied onto the first surface of the wafer so as to completely cover the bond wires and pads of the semiconductor units.

Abstract: The present invention includes a package for housing an integrated circuit device. The present invention also includes leadframes and methods for making such packages. In one embodiment, the package includes an integrated circuit device on a metal die pad. A metal ring is between the die pad and leads and surrounds the die pad. The ring is connected to the die pad by a nonconductive adhesive tape. Encapsulant material covers the entire structure, except for portions of the leads. The ring is electrically connected to a lead identified for connection to an external power voltage supply. The ring in turn is electrically connected to a power voltage input pad on the integrated circuit device. The potential of the die pad may float, or the die pad may be electrically connected through a lead to an external ground voltage. The package is made from a leadframe that has a die pad, a metal ring between the die pad and radiating leads, and a nonconductive adhesive tape that connects the ring to the die pad.

Abstract: Methods of making integrated circuit device packages and substrates for making the packages are disclosed. An embodiment of a method of making a substrate includes providing an unpatterned sheet of polyimide material having a first surface and an opposite second surface. A planar metal layer is attached to the second surface of the polyimide sheet. The metal layer is patterned to form an array of package sites, with each site including a planar die pad and planar leads. Apertures are formed through the polyimide sheet, either before or after attaching the metal layer. Each aperture is juxtaposed with a lead allowing access thereto. A method of making a package using the substrate includes mounting an integrated circuit device above the die pad (e.g., on the substrate or on the die pad through an aperture in the substrate). Bond wires are connected between the integrated circuit device and the leads through the apertures.

Abstract: A method of making an integrated circuit package is disclosed. A conductive first adhesive is applied onto a leadframe pad of a leadframe. A conductive second adhesive is applied on an input portion of the leadframe, such as a leadframe member that is integral with inner portions of input leadfingers. An integrated circuit die, such as a power MOSFET, is placed on the first adhesive on the leadframe pad. A conductive third adhesive is applied onto a surface of the integrated circuit die opposite the leadframe pad. A conductive strap is placed on the third adhesive on the integrated circuit die and on the second adhesive on the leadframe. The first, second and third adhesives are then simultaneously cured so that the integrated circuit die is permanently attached to the leadframe pad, and the conductive strap is permanently attached to the die and the leadframe member.