Abstract: An analog voltage pulse generator, including a first break-over component of Shockley diode type to activate a rising edge of a pulse on an output terminal and a second component of thyristor type to block the first component and deactivate the pulse.

Abstract: A method for manufacturing a semiconductor device having improved adhesion at an interface between layers of dielectric material, comprising the steps of forming a first layer of dielectric material on at least one part of a structure defined in a semiconductor substrate and forming a second dielectric material layer superimposed on the least one part of the first layer. The method further includes the step of forming, in the part where the first and second layers are superimposed, an intermediate adhesion layer comprising a ternary compound of silicon, oxygen and carbon. The formation of the adhesion layer takes place at low temperature and in an atmosphere kept essentially free of oxidative substances different from those serving to provide the silicon and the carbon to the layer. Preferably the layer is formed by the plasma enhanced chemical vapour deposition technique.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: An area-efficient reconstruction filter removes undesirable sample images produced by current-driven digital-to-analog converters. The reconstruction filter includes: an input node for receiving the input current signal; an operational amplifier having first and second inputs and an output at which the output voltage signal is produced; a first resistor coupled between the output of the operational amplifier and the input node; a second resistor coupled to the first input of the operational amplifier; and a third resistor coupled between the input node and the second resistor. The reconstruction filter may also include a fourth resistor coupled between the input node and a reference voltage.

Abstract: An adapter device for assisting debugging of a microprocessor on a single integrated circuit chip, the integrated circuit chip comprising an on-chip CPU with a plurality of registers, a communication bus providing a parallel communication path between the CPU and a first memory local to the CPU and an external communication port connected to the said bus on the integrated circuit chip, the communication port having an internal connection to the said bus of an internal parallel signal format and an external connection to the adapter unit of a first external format less parallel than the said internal format; the adapter device comprising a first communication unit for connection to the communication port with the first external format; a second communication unit for connection to an external computer device with a second external format having a higher latency than the first external format; a second memory local to the adapter device; and a processing unit local to the adapter device and operable: (a) in a f

Abstract: The present invention relates to a latch including two first N-channel transistors connected to a low supply potential and controlled by a clock signal; two second transistors respectively connecting the two first transistors to an inverted output terminal and to a non-inverted output terminal and respectively controlled by a data line and a complementary data line; two third P-channel transistors respectively coupling the two second transistors to a high supply potential and cross-controlled by the output terminals; and circuitry for maintaining the states of the output terminals when the first transistors are non-conductive.

Abstract: An integrated circuit including serial data input and output pins, on-chip functional circuitry and test logic, a test access port controller, and a data adaptor. The test access port controller is connected to effect communication of serial data across tile chip boundary via the input and output pins and is connectable to the test logic to effect communication of serial test data off-chip. The data adaptor is connectable to the input and output pins via the test access port controller. The data adaptor includes an interface for communicating data in the form of serial bits with the test access port controller under control of a first clock signal, and an interface for communicating data in the form of successive sets of parallel data and control signals with the on-chip functional circuitry under control of a second clock signal that is generated independently of the first clock signal.

Abstract: A sense amplifier circuit has two inputs for connection to complementary bit lines and an output terminal. The circuit comprises control circuitry responsive to control input for selectively tristating the output terminal.

Abstract: A method for producing an isolation region on a surface of a semiconductor substrate includes: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling layer over the masking layer and the isolating layer, so that it completely fills the notch; forming field protection spacers adjacent to the masking layer; partially removing the filling layer to expose the upper surface of the isolation layer, the notch remaining filled with a part of the filling layer; and selectively etching the isolating layer from its upper limit until this upper limit is substantially coplanar with the upper surface of the semiconductor substrate. A transistor may be produced in a semiconductor substrate, having a minimum gate length, a minimum width isolation region and wide field isolation region.

Abstract: The invention provides an apparatus for decoding a coded digital data sequence. The apparatus includes a first Viterbi decoder of a first response type, a first filter and a second filter. The first and second filters are coupled to receive decoded sequences from the first Viterbi decoder. The first Viterbi decoder generates a first decoded sequence from the coded digital data sequence. The first and second filters generate respective first and second error signals in response to receiving the first decoded sequence. The first and second error sequences indicate differences between the first decoded sequence and second and third decoded sequences, respectively. The second and third decoded sequences are probable sequences produced by Viterbi decoders of respective second and third response types in response to receiving the coded digital data sequence.

Abstract: A switching circuit is discussed that has an improved switching time in comparison with switching circuits of a known type. The circuit comprises three switches connected in series, the first switch being connected to an upper power supply and the third switch being connected to a lower power supply. The output of the circuit is connected to a circuit node located at the connection between the second and third switch. The input to the switching circuit is also connected to the third switch and additionally connected to a control circuit which provides a further output to control the first switch. The second switch is responsive to the voltage at the circuit node such that the second switch only conducts when the voltage at the output node falls below the upper supply voltage.

Abstract: The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.

Abstract: An inkjet print head includes an ink drop emission mini-gun and a drop emission sensor integrated in a chip of semiconductor material. The mini-gun is formed by an ink chamber and a nozzle in communication with the ink chamber and the drop emission sensor includes a resistive element arranged in a position adjacent to the ink chamber. The resistance of the resistive element depends on the pressure exerted thereon, so that when the mini-gun emits an ink drop, it is subjected to a recoil movement which causes a change of pressure and hence of resistance in the resistive element; this change in resistance may be detected through suitable circuitry to identify whether and when a drop of ink has been emitted.

Abstract: A circuit for providing a control signal for a load includes a first switch having a first and a second state, a second switch having a first and a second state coupled to said first switch, a load connected to said first and second switches, protection circuitry for protecting said load from excessive voltage and circuitry for switching said first switch. The circuit is arranged so that when the first switch is in the first state current flows from the load to the first switch and the switching circuitry is arranged to switch the first switch to the second state when the voltage across the load reaches a predetermined value.

Abstract: A circuit for generating an output voltage proportional to temperature with a required gradient, the circuit including a first stage arranged to generate a first voltage which is proportional to temperature with a predetermined gradient but has a positive value when the temperature falls below zero and a second stage connected to the first stage and including a differential amplifier having a first input connected to receive the first voltage and a second input connected to receive a feedback voltage which is derived from an output signal of the differential amplifier via an offset circuit which introduces an offset voltage such that the output signal of the differential amplifier provides at an output node the output voltage which has a negative variation with negative temperatures.

Abstract: A circuit for generating an output voltage which is proportional to temperature with a required gradient is disclosed. The circuit relies on the principle that the difference in the base emitter voltage of two bipolar transistors with differing areas, if appropriately connected, can result in a current which has a positive temperature coefficient, that is a current which varies linearly with temperature such that as the temperature increases the current increases. It is important to maintain a stable internal line voltage in the face of significant variations in a supply voltage to the circuit. This is achieved herein by providing control elements appropriately connected to a differential amplifier. The stable internal supply voltage can be used to power a subsequent stage of the circuit for fine control of the gradient of the voltage proportional to temperature.

Abstract: A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an opening; annealing to form a third thin oxide layer and harden the second oxide layer; implanting a P-type dopant; depositing a fourth silicon nitride layer; depositing a fifth silicon oxide layer and etching it; anisotropically etching the fifth, fourth, and third layers; performing cleanings during which the fifth layer is reetched and takes a flared profile; depositing a sixth polysilicon layer; and implanting an N-type dopant.

Abstract: The present invention relates to a one-time programmable (OTP) device including three fuses connected in parallel to a logic element which determines that the device is programmed when at least one of the fuses open. The present invention comprises a one-time programmable device that, before the one-time programmable device is programmed, provides, in response to a test signal, a simulation output signal that simulates an output signal that the one-time programmable device provides if the one-time programmable device is programmed.

Abstract: A computer system including at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints including a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints and a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, and a first comparator, having inputs coupled to the precondition register, that compares at least one precondition code in the set of precondition codes with a first data value in the computer system and provides a signal to the action register in response thereto. A method of triggering a watchpoint in a computer system is also provided.

Abstract: High density MOS technology power device structure, including body regions of a first conductivity type formed in a semiconductor layer of a second conductivity type, wherein the body regions include at least one plurality of substantially rectilinear and substantially parallel body stripes each joined at its ends to adjacent body stripes by junction regions, so that the at least one plurality of body stripes and the junction regions form a continuous, serpentine-shaped body region.