Abstract: The present invention relates to a conductive line on an integrated circuit. The integrated circuit includes an insulating layer in which is formed several grooves of predetermined width. The conductive line includes a first interconnection layer having a first thickness and a second interconnection layer having a second thickness. The predetermined width is greater than twice the greatest of the two thicknesses, and smaller than twice the sum of the thicknesses.

Abstract: A data reception unit for receiving a plurality of data streams over a data chanel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a reserve buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation-based on the identity portion.

Abstract: A method of fabricating a tungsten contact in a semiconductor device comprises providing an oxide layer on a region of a silicon substrate; depositing a sealing dielectric layer over the oxide layer; and depositing an interlevel dielectric layer over the sealing layer. The interlevel dielectric layer, the sealing dielectric layer and the oxide layer are then etched through as far as the substrate thereby to form a contact hole and to expose the said region. A dopant is implanted into the said region whereby the implanted dopant is self-aligned to the contact hole. The substrate is thermally annealed. Tungsten is selectively deposited in the contact hole and an interconnect layer is deposited over the deposited tungsten contact. The invention also provides a semiconductor device which incorporates a tungsten contact and which can be fabricated by the method.

Abstract: A memory system comprises a memory array having a plurality of memory locations; a plurality of write ports for writing to the memory array; write protection circuitry for preventing more than one memory location from being addressed at the same time in a write operation, the write protection circuitry providing one write enable signal for each write port, the write enable signals being applied to the memory array; and circuitry for controlling the timing of the application of the write enable signals to the memory array, the circuitry for controlling the timing being upstream of the write protection circuitry.

Abstract: A power component formed in an N-type silicon substrate, the lower and upper surfaces of which respectively include a first and a second P-type region that do not extend to the component periphery, a high voltage being capable of existing between the first and second regions and having to be withstood by the junctions between the first and second regions and the substrate. A deep insulating region that does not join the first region is provided at the lower periphery of the component, the lower surface of the substrate between said deep insulating region and the first region being coated with an insulating layer, the height of the deep insulating region being greater than that of a possible soldering upward extension formed during the soldering of the lower surface on a heat sink.

Abstract: A test circuit for memory having plural memory cells and address latches responsive to addressing circuitry for reading/writing to said memory cells in a normal mode, has first connecting circuitry for connecting the address latches to form a linear feedback shift register. The linear feedback shift register is responsive to a clock signal to provide a sequence of addresses for testing the memory in a test mode.

Abstract: A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a second heavily-doped P-type area separate from the second area; forming at the periphery of this second area a third N-type area; forming by epitaxy a second silicon layer; forming a deep trench crossing the first and second silicon layers, penetrating into the substrate and laterally separating the second area from the third area; and performing an anneal such that the dopant of the third area is in continuity with that of the first area.

Abstract: A method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of depositing a protective layer; depositing a covering layer; opening the protective and covering layers at a location substantially corresponding to the desired border of the two areas; forming a spacer along the side of the opening, this spacer having a rear portion against said border and an opposite front portion; opening the protective and covering layers behind the rear portion of the spacer; and removing the protection layer to reach the rear portion of the spacer; whereby two self-aligned areas are defined on either side of the spacer length.

Abstract: An integrated circuit comprising a logic processor and a fuzzy logic coprocessor is disclosed which processes a plurality of analog inputs. The logic processor and fuzzy logic processor are combined in the form of a single integrated circuit. The integrated circuit accepts a plurality of analog inputs which are digitized and provided as output to a display peripheral or are used to control an actuator peripheral such as a control unit for a valve. The integrated circuit includes means for loading or exchanging informational elements with other units of an installation.

Abstract: A circuit, for digitizing an analogue signal includes an analogue to digital converter, a clip processor adapted to estimate a value for clipped digital signal samples, and a buffer adapted to dynamically store a plurality of digitized samples produced by the analogue to digital converter. The clip processor is adapted to read digitized samples from the buffer and replace clipped digitized samples with the estimated values, thereby mitigating the effects of clipping in an output of the circuit.

Abstract: A circuit that synchronizes an output clock signal to a second clock signal includes a frequency locked loop circuit that receives the output clock signal and the second clock signal, modifies a frequency of the output clock signal in response to a difference in frequency between the output signal clock signal and the second clock signal to provide an output clock signal having a frequency within a predetermined error band of the frequency of the second clock signal and wherein the frequency locked loop continues to provide the output clock signal in the absence of the second clock signal.

Abstract: An apparatus and method for determining a minimum clock delay provided to sense amplifiers of a memory array. The method first determines a response time of the overall memory circuit by varying the delay of an external clock until the output of the memory circuit is just valid. Then an externally provided sense amplifier clock is substituted for the internal sense amplifier clock and the instant of application of the externally provided sense amplifier clock is varied until the circuit output is just valid.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.

Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

Abstract: A MOS capacitor comprises a semiconductor substrate, a first well region of a first conductivity type formed in the substrate, at least one doped region formed in the first well region, and an insulated gate layer insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.

Abstract: A method of manufacturing a unipolar component of vertical type in a substrate of a first conductivity type, including the steps of: forming trenches in a silicon layer of the first conductivity type; coating the lateral walls of the trenches with a silicon oxide layer; filling the trenches with polysilicon of the second conductivity type; and annealing to adjust the doping level of the polysilicon, the excess dopants being absorbed by the silicon oxide layer.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: A bidirectional switch, including a first bidirectional switch between two power terminals of the switch, a low-voltage storage element between a first power terminal and a control terminal of the switch, and a control stage adapted to cause, upon each halfwave beginning of an A.C. supply voltage applied between the power terminals and when the switch is on, the charge of the storage element with a biasing depending on the sign of the halfwave.

Abstract: A testing circuit made on a silicon wafer including a plurality of identical cells, each of which includes a primary capacitor of given characteristics, which includes a test capacitor of same characteristics as each primary capacitor and of surface at least equal to the sum of the surfaces of the primary capacitors.