Abstract: Clock generation circuitry 1300 includes an oscillator 1302 for generating a first signal from a crystal 1301 of a selected oscillating frequency. A first frequency multiplier 1304 selectively multiplies the frequency of the first signal by a predetermined factor to obtain a second signal having a frequency of a preselected multiple of a first set of clock signals. A divider 1305 selectively divides the frequency of the second signal by a second factor to obtain a third signal of a selected frequency.

Abstract: A noise shaper including a filter system for generating a first set of poles and zeros characterizing noise attenuation in a signal baseband of a noise transfer function and at least one additional set of at least one pole and one zero characterizing noise attenuation in at least one additional band outside the baseband of the noise transfer function.

Abstract: A method of preparing a set of items for future business processes includes the step of grouping the items to be included in the set, each of the items associated with a unique identifier. The unique identifiers are then recorded en masse and communicated to a database. A set identifier is then generated from the recorded identifier and associated with the set of items.

Abstract: A method of controlling a power supply having an output activated in response to a first logic level of a control signal and deactivated in response to a second logic level of the control signal. A clock is generated on a second power source and used to time a time-out period of a selected number of clock periods. In response to the step of sensing, if the state of the output of the power supply is inactive through the timeout period, then the first logic level of the control signal is generated to activate the power supply for use in powering operations of an associated device. After completion of these operations, the second logic level of the control signal is generated to deactivate the power supply. If however, the state of the output of the power supply is active during the time-out period, then the first logic level of the control signal is maintained to power operations of the associated device.

Abstract: An embedded system includes a microprocessor and performance measuring logic coupled to the microprocessor and configured to record selected performance metrics. In the given routine. In general, a counter is configured to record statistics for each of the performance metrics, and the counters may be controlled using a programmable mask, which is included in a memory coupled to the microprocessor. Based on these metrics, designers may fine-tune software for the embedded system.

Abstract: A method of performing sample rate conversion in a data converter operating from an oversampling clock corresponding to a native sample rate and a native oversampling factor. A virtual sample rate and a virtual oversampling factor are selected proportional to the native sample rate and the native oversampling factor. A data stream having a data sample rate is sampled by the virtual oversampling factor. The data stream is also resampled with a resampling ratio approximating a ratio of the data sample rate to the virtual sample rate.

Abstract: A delta-sigma data converter includes a first quantizer responsive to outputs of first and second loop filters, the first quantizer introducing a quantization error during quantization. The first loop filter is responsive to an output of the first quantizer. A second quantizer quantizes an error data stream representing the quantization error introduced by the first quantizer. The second loop filter includes an integrator for integrating a quantized error data stream output from the second quantizer. An analog output path responsive to the output of the first quantizer and an output of the integrator generates the converter output.

Abstract: An audio system 100 includes circuitry 116 for generating an audio data stream and circuitry 103 for generating digital words defining a volume control level. System 100 also includes volume control circuitry 5000 for controlling the amplitude of the audio data stream in response to the digital words. Volume control circuitry 5000 includes a master register 5001 for holding digital words received from circuitry for generating 116 and a slave register 5002 for holding a digital word selectively transferred from master register 5001 in response to an enable signal. Output control circuitry 5005, 5006 and 5007 receive the audio data stream and apply a preselected gain defined by the digital word held in slave register 5002. Volume control circuitry 5000 also includes circuitry 5003, 5004 for generating the enable signal when a digital word held in the master register 5001 changes and the audio data stream output from ouput control circuitry 5005, 5006, 5007 reaches a zero crossing.

Abstract: An integrated circuit 300 included a plurality of circuit blocks 202-206 for selectively performing data processing operations in response to a set of instructions. Circuitry 301 dynamically activates and deactivates selected ones of circuit blocks 202-206 during the execution of the set of instructions.

Abstract: A converter for converting digital data into differential analog signals includes a temperature and process independent bias voltage generator for generating a bias voltage and a digital to differential converter for converting a digital word into differential voltages. The digital to differential converter includes a first switching circuitry controlled by the digital word for selectively coupling a first output node to the bias voltage and a second output node to a supply voltage. Second switching circuitry controlled by a complement of the digital word selectively couples the first output node to the supply voltage and the second output node to the bias voltage. The first and second pairs of switches substantially simultaneously conduct at a desired differential cross-over voltage at the first and second output nodes based on the choice of the bias voltage such that the digital to differential analog converter operates from the operating voltage to the operating voltage plus the bias voltage range.

Abstract: A soft cache system compares tag bits of a virtual address with tag fields of a plurality of soft cache register entries, each entry associated with an index to a corresponding cache line in virtual memory. A cache line size for the cache line is programmable. When the tag bits of the virtual address match the tag field of one of the soft cache entries, the index from that entry is selected for generating a physical address. The physical address is generated using the selected index as an offset to a corresponding soft cache space in memory.

Abstract: A switched capacitor circuit 300, including a sampling capacitor 303, switches 301, 304 for charging the sampling capacitor 303 during a charging phase, and switches 302, 305 for transferring charge from the sampling capacitor 303 to a load 313 in the feedback loop of an operational amplifier 312 during a dump phase. Circuitry 701 controls the discharge of sampling capacitor 303 during the dump phase to minimize transients at the input of the operational amplifier 312 and thereby minimize input threshold voltage variation.

Abstract: An integrated analog to digital and sample rate converter 206 includes sampling circuitry 207 for receiving an analog signal and generating a single or multibit stream of digital signals at a first rate. A leaky integrator filter 208 removes quantization noise from the stream of samples such that resampling can be carried out. Circuitry 209/210 resamples the filtered stream of samples output from leaky integrator filter 208 to generate an output stream of samples at a second rate.

Abstract: A personal accessory includes an outer cover and a pocket disposed within the body and accessible through an aperture through the outer cover. A holder includes a peripheral frame defining at least one window for receiving and holding a substantially flat object, the holder adapted to be inserted into and extracted from the pocket. A tether has a first end attached to the body at a point within the pocket and a second end attached to the holder, the holder rotatable around the second end of the tether when the holder is substantially extracted from the pocket. A quick release mechanism is selectively provided within selected pockets of the personal accessory and includes a corresponding plurality of pocket liners attached to a rigid sheet. Manual force applied to the rigid sheet forces substantially flat objects within the selected pockets outward from those pockets for rapid access and extraction.

Abstract: Metastable compensation circuitry 700 for detecting and compensating for metastable states of a regenerative latch 209 in a charge redistribution analog to digital converter 201. First and second latches 701a,b each having a selected threshold voltage for monitor corresponding first and second outputs of regenerative latch 209. Detection logic 202a,b 703 detects a selected output state of the first and second latches corresponding to a metastable state of regenerative latch 209. Suppression logic 703 generates an output of a selected logic level in response to the detection of a metastable state by detection logic 702/703.

Abstract: A content addressable memory cell 920 includes a first storage element 922a for storing information and a first transistor 921a for selectively transferring charge representing information from a first bitline 924a to the first storage element 922a. A second transistor 921b selectively transfers charge representing information from a second bitline 924b to a second storage element 922b. First and second comparelines 925a, 925b carry first and second bits of a comparand to a comparator 905, 906, 908 which compares the first and second bits of the comparand with information stored on the first and second storage elements. In response, comparator 905, 906, 908 selectively controls a voltage on a corresponding one of a plurality of matchline 909.

Abstract: A system and method for compensating switched mode amplifiers. The amplifier system includes an adaptive filter coupled to the output of circuitry that recovers the analog signal from the output of the switching amplifier circuitry. The adaptive filter derives an inverse transfer function of the forward path through the system. The derived inverse transfer function is used to generate a coefficient map which a compensation filter responsively compensates for from variations in the output load of the amplifier system. In the disclosed method, the deriving the inverse transfer function may further include calibrating the adaptive filter continuously, at system startup or in response to user demand.

Abstract: A method and a circuit of performing an analog to digital conversion in a charge redistribution circuit including a capacitor array of weighted capacitors and a transistor track switch for sampling an input signal into the capacitor array. A common mode voltage is stepped to a voltage sufficient to turn on the transistor track switch during a sampling phase. During the sampling phase, a top plate of each of the capacitors is coupled to the common mode voltage through the track switch while the bottom plate of each of the capacitors is coupled to an input to sample an input signal. During a conversion phase, the top plate of each of the capacitors is decoupled from the common mode voltage and the bottom plates of a selected one of the weighted capacitors is coupled to a first reference voltage, a weight of the selected one of the weighted capacitors proportional to the step in the common mode voltage.

Abstract: A method of operating a cache memory includes the step of storing a set of data in a first space in a cache memory, a set of data associated with a set of tags. A subset of the set of data is stored in a second space in the cache memory, the subset of the set of data associated with a tag of a subset of the set of tags. The tag portion of an address is compared with the subset of data in the second space in the cache memory in that said subset of data is read when the tag portion of the address and the tag associated with the subset of data match. The tag portion of the address is compared with the set of tags associated with the set of data in the first space in cache memory and the set of data in the first space is read when the tag portion of the address matches one of the sets of tags associated with the set of data in the first space and the tag portion of the address and the tag associated with the subset of data in the second space do not match.