Abstract: An audio system 100 disposed on a single chip includes an output mixer 115 having inputs for receiving first digital audio data of a first bit width from a first digital-to-analog converter 110, digital audio data of a second bit width from a second digital-to-analog converter 6601, and analog data from an external port. An output port drives an analog signal output from the output mixer. An input mixer 114 has inputs for receiving analog data from a plurality of sources and analog-to-digital converters 111 to convert an analog output from the input mixer into digital data. An input path transmits the digital data output from the analog to digital convertors 111 to an external digital bus.

Abstract: A variable color light emitting diode digital display system automatically exhibits integers and decimal numbers in different colors. A logic circuit is provided for detecting the presence or absence of a decimal point in a string of digits. The color of the exhibited digits is controlled in accordance with the detection.

Abstract: A cover 30 for a selected dental hand piece 10 includes a body 32 having first and second halves 34a, 34b of a shape and dimensions selected to substantially conform with a shape and dimensions of selected hand piece 10, said halves. Hinge 36 couples the first and second halves 34a, 34b of body 32 for allowing the first half 34a to rotate with respect to the second half 34b to thereby form an enclosure for enclosing a substantial portion of hand piece 10. The enclosure includes a head portion 42, handle portion 32 and a substantially rigid neck portion 40 between handle portion 32 and head portion 42.

Abstract: Audio data processing circuitry 300 includes a plurality of analog inputs 101 for receiving analog audio data and a digital input 105 for receiving digital audio data. A analog mixer 312 mixes analog data received at said plurality of analog inputs 101 to generate a mixed analog audio stream. An analog-to-digital converter 313 converts the mixed analog audio stream to a digital audio stream and a digital mixer 315 mixes digital data received at the digital input 105 with the digital audio stream from the analog mixer 312 to generate a mixed digital audio stream.

Abstract: Memory 900 includes an array 401 of rows and columns of memory cells, each row associated with first and second wordlines and each column associated with first and second bitlines. A first port (PORT1) is utilized for accessing selected ones of the memory cells using the first wordline and the first bitline of corresponding ones of the rows and columns, first port (PORT1) associated with first dedicated sets of address, data, clock and control signal terminals for supporting accesses via first processing device 101 using a time base and an access-type required by such first processing device. A second port (PORT2) is utilized for accessing selected ones of the memory cells using the second wordline and the second bitline of corresponding ones of the rows and columns, second port (PORT2) associated with second dedicated sets of address, data, clock and control signal terminals for supporting access by a second processing device 1002.

Abstract: A memory 1300 including an array of rows and columns of memory cells 501 is disclosed. For each column, first and second interdigitated bitlines 1301, 1303 are coupled to the cells of the column. The first bitlines 1301 has an end coupled to a sense amplifier 1302 at a first boundary of the array and a second bitline 1303 has an end coupled to a second sense amplifier at a second boundary of the array, the first and second boundaries being spaced apart by the array. Control circuitry 508 precharges the first bitlines 1301 of the columns of the array substantially simultaneous to an access to the array through the second bitlines 1303 of selected columns of the array.

Abstract: A method of processing a stream of audio information received by a multiple processor audio decoder. Processing operations are performed by a first processor on the stream of audio information to produce at set of results. The first processor writes the set of results into a shared memory and a flag is set indicating that the results are ready. In response to the flag, a second processor reads the results from shared memory. When the results have been read from shared memory, the second processor sends a command to the first processor. The first processor then clears the flag.

Abstract: An improved method and apparatus for anchoring tensioning members in a concrete structure and the like wherein there is provided a wedge support member having wedge-receiving pockets coaxially aligned with the anchor seats in an anchorage block permitting the anchorage wedges to first be inserted into the pockets not allowing the tensioning members to slip during tensioning. This method is used in post-tensioning of monostrand cable. The apparatus anchors the tensioning members by installing wedges into their respective wedge seats. A magnetic tip is utilized to hold the wedges in place while a slide hammer provides and transmits the energy to forcibly insert the wedges.

Abstract: A memory 700 having an array 701 of rows and columns of dynamic memory cells 301, cells 301 of each row coupled to a refresh wordline 303a and an access wordline 303b and cells 301 of each column coupled to a refresh bitline 302a and an access bitline 302b. Refresh circuitry 711, 712, refreshes selected rows of cells corresponding to a refresh wordline 303a and a corresponding one refresh bitline 302a. Access circuitry accesses selected cells of a selected row using corresponding access wordline 303b and corresponding one of the access bitlines 302b. The access circuitry includes a new address detector of 709 for detecting receipt of a new address of said memory, a row decoder 702 for selecting access wordline in response to receipt of the new address and access sense amplifiers 703 and an access column decoder 704 accesses at least one cell along the selected wordline 303b using the corresponding access bitline 302b.

Abstract: A dynamic random access memory 400 includes an array 401 of physical rows and columns of memory cells, the cells of each row coupled to first and second wordlines 603 and first and second bitlines 602. A direct input/output data path 402 having a width equal to a width of the rows supports simultaneous writing to each of the cells along a selected row using the first wordlines and first bitlines during a single access cycle without restore.

Abstract: A data processing system having a DRAM and a non-volatile memory, such as a ROM or a programmable ROM (PROM), is implemented on a single integrated circuit using DRAM data processing techniques. The DRAM is manufactured in accordance with known processing techniques. The non-volatile memory is manufactured using the same DRAM manufacturing techniques, with the addition of a processing step in which a first terminal of a stacked capacitor manufactured in accordance with the DRAM process, is coupled to a known-reference voltage. This stacked capacitor structure may be coupled to a known conductor through the formation of a via and the subsequent coupling of a conductor to the stacked capacitor structure through the via. Alternatively, the stacked capacitor structure may be coupled to the known reference voltage through an internal connection to that reference voltage.

Abstract: A tape feeder 200 includes a sprocket 201 having a plurality of teeth 202 for engaging holes of a tape. A pawl 205 engages selected teeth of sprocket 201. A first lever 203 is coupled to pawl 205 and a second lever 204 is coupled to first lever 203 and a source 208 of a driving force. First lever 203 and second lever 204 operate by a toggle action to selectively engage pawl 205 with ones of teeth 202 and thereby index sprocket 201.

Abstract: A multiprocessor processing 200 includes a memory system having a memory controller 202 for linking a plurality of processors 201 with an integrated memory 203. Integrated memory 203 comprises a plurality of static random access arrays 603 and a dynamic random access 407.

Abstract: The method of mounting a semiconductor device 200 on a supporting structure 101, the semiconductor device having a surface 201 including a defined area 202 for receiving photons and a plurality of conductors 203/204 for establishing connections to the device. An aperture 301 is formed through the supporting structure, the aperture sized to correspond to a size of the defined area of the semiconductor device. Conductors 302 are formed on the supporting structure adjacent to the aperture in a pattern corresponding to the pattern of the conductors on the semiconductor device. The semiconductor device is mounted to the supporting structure such that the conductors on the semiconductor device contact the conductors on the supporting structure where the defined area of the semiconductor device is exposed to photons through the aperture.

Abstract: An optical memory 200 including an optical storage element 301 for storing data as a packet of photons, optical storage element 301 delaying in time the packet of photons traveling through the storage element from a first point to a second point. A photon source 302 receives an electrical signal representing data and injects the packet on to optical storage element 301 in response, and a detector 303 selectively detects the packet traveling on optical storage element 301. A feedback path 306/305 couples photon source 302 and detector 303 for recirculating the packet through storage element 301.

Abstract: A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325. The system CPU initiates data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the graphics engine 325. In an alternate embodiment, the subsystem includes a subsystem master control unit or MCU to enable parallel or simultaneous operation of the Host XY unit and the graphics subsystem MCU.

Abstract: Display control circuitry is provided which includes a frame buffer 104 having a plurality of memory spaces 301 each for storing a block of display data. Circuitry 200 is provided for generating display position data representing a position on a display screen corresponding to a current display pixel being generated. For each memory space 301, a window control circuit 201 is provided for controlling the transfer of a block of data from the given memory space 301 to a selected window on the display screen. Each window control circuit 201 includes first registers 205, 206 for storing data defining horizontal boundaries of the window, second registers 210, 211 for storing data defining vertical boundaries of the window, and circuitry 207, 208, 209, 212, 213, 214 for comparing the display position data with data stored in the first and second registers and generate an enable signal when the position on the screen of the current pixel is within the window boundaries.

Abstract: A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a message is written into a second register with the first processor. The pending flag is set to a second selected logic state with the first processor and an interrupt to the second processor is generated. The message is read from the second register with the second processor when the pending flag is in the second logic state. The pending flag set to the first logic state with the second processor.

Abstract: A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.

Abstract: An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.