Abstract: A shift register includes a plurality of shift register stages having inputs and outputs coupled to form a chain. Each stage includes enable and disable control inputs, with an output of a selected one of the stages coupled to the enable input of a stage a selected number of stages ahead in the chain and to the disable input of a stage a selected number of stages behind in the chain.

Abstract: A sample rate converter 210, 209 includes a filter 210 for processing digital data in response to a clock controlled by a clock enable signal, the filter 210 receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry 209 generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.

Abstract: Disclosed in this application is the placement of an additional integrator between the first stage integrator output and the input to the attenuator/low pass filter. This approach reduces the input referred offset by a factor equal to the gain of the additional integrator, and the offset of the additional integrator itself will be divided by the gain of the first-stage integrator.

Abstract: An interface 400 for interfacing an optical pickup 101 is associated with processing circuitry 100. A plurality of inputs receive data retrieved from an optical disk by the pickup and 401, 402, 403 are each coupled to a corresponding one of the inputs and independently activated and deactivated to selectively pass the data to the processing circuitry.

Abstract: A portable radio telephone handset includes the capability of operating as a data transfer terminal as well as an analog cellular telephone subscriber station. Two modes of operation are available in the handset, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode. A paging function for incoming analog cellular communication is carried out on a CDPD channel. The handset distinguishes between paging signals identifying CDPD mode communications and paging signals identifying analog cellular communications. The handset automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS configuration. To maintain the security of the handset ID, AMPS communications can be set up and controlled using CDPD control channels.

Abstract: An interface for coupling a modem port with a transmission line includes a hybrid converter having a variable gain amplifier coupling a transmit path of a first differential polarity and a received path of a second differential polarity.

Abstract: A portable radio telephone handset includes the capability of operating as a data transfer terminal as well as an analog cellular telephone subscriber station. Two modes of operation are available in the handset, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode. A paging function for incoming analog cellular communication is carried out on a CDPD channel. The handset distinguishes between paging signals identifying CDPD mode communications and paging signals identifying analog cellular communications. The handset automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS configuration.

Abstract: A multicolor display element includes a plurality of display areas arranged in a pattern, each including light emitting diodes of respective primary colors, which are coupled to the buses in accordance with their colors. A single enable input is provided for receiving an enable signal having an active level and an inactive level, for selectively extinguishing the entire display element and for illuminating the selected display areas in a desired color. The enable input jointly controls the conductivity of tri-state buffers which are respectively coupled to the buses.

Abstract: An optical disk pickup system 400 using current mode signal transmission is disclosed. An operational amplifier 404 has an input for receiving an electrical signal and a feedback loop including a current path of a first transistor 405 of a first size, transistor 405 having a control terminal at a preselected voltage. A conductor 402 is coupled to an output of operational amplifier 404 for transmitting the electrical signal as a current. A second transistor 406 of a second size has a current path in series with a conductor 402 and a control terminal coupled to the preselected voltage, transistors 405, 406 forming a current divider.

Abstract: A method of dynamically adjusting a multiple stage pipeline to execute one of a set of instructions, wherein each stage has a latency and performs a selected data operation. An instruction to be executed is received and a number of stages of the pipeline is selected to execute the instruction as needed to perform a corresponding data operation. Unnecessary stages are bypassed to a reduced latency and the instruction is executed with the selected stages.

Abstract: A hinged cap with a cap body having a raised portion with an outlet opening in its upper boundary wall, a hinged lid connected via a hinge to said cap body, and a locking arrangement formed on cap body and on hinged lid. At least the raised portion is formed of an elastically deformable material, and the hinged lid positions tight against at least the lip of the outlet opening in a closed position, exerting pressure on the raised portion in the direction of closure. An element formed of an elastically deformable material is provided on the hinged connection which generates a biasing between the cap body and the hinged lid in order to bring the hinged lid into an opened position.

Abstract: A memory 200 includes a first memory segment 302 comprising an array of rows and columns of memory cells, a selected column of cells in the first segment 302 accessed through a dedicated sense amplifier 304 associated with the first segment. A second memory segment 302 comprises an array of rows and columns of memory cells, a selected column of cells in the second memory segment 302 accessed through a dedicated sense amplifier 304 associated with the second segment. A Read Input/Output line 306a is coupled to the sense amplifier accessing the selected column of the first segment 302 for reading data from the first segment during a selected access cycle. A Write Input/Output line 306b is coupled to the sense amplifier 304 accessing the selected column of the second segment 302 for simultaneously writing data to the second memory segment 302 during the selected access cycle.

Abstract: A signal generator 600 includes oscillator circuitry for generating first and second signals having a selected phase relationship and an interpolator 610 for interpolating between a phase of the first signal and a phase of the second signal to generate a third signal having a phase between the phases of the first and second signals.

Abstract: A bracket 107 for retaining a stair rod 106 includes a first portion 301b for affixing to a stair including means 304 for securing a finial thereto and a seat 301/302 for receiving an end of the corresponding stair rod 106. A second portion 301b is rotatably coupled to the first portion 301a and includes means for retaining the end of corresponding stair rod 106 in the seat of the first portion 301a of bracket 107. Means 402 are also provided for holding the first and second portions of the bracket in engagement.

Abstract: A voltage out-of-calibration detector 200 includes a voltage divider operating between first and second voltage rails and having a plurality of taps 203 for generating first and second comparison voltages. A first set of switches 205 selectively couples at least one of the plurality of taps 203 to the input of a first voltage comparator 401a, first voltage comparator 401a comparing the first comparison voltage with an input voltage and outputing a signal when the input voltage exceeds the first comparison voltage. A second set of switches 206 selectively couples at least one of the plurality of taps 203 to an input of a second voltage comparator 401b, second voltage comparator 401b comparing the second comparison voltage with the input voltage and outputing a signal when the input voltage is below the second comparison voltage. Control logic 300 selectively activates the first and second sets of switches 205/206 in response to received control signals.

Abstract: An audio system 100 includes digital-to-analog converters 110 having left and right paths for converting received left and right streams of digital audio data and a plurality of analog data ports for receiving left and right channel streams of analog audio data. Mixer 115 has left and right paths for selectively mixing left and right channel data passed from converters 110 and left and right channel data passed from the analog data ports. Muting circuitry is also provided for selectively muting said right and left channel data to be passed to mixer 115 from converters 110. Circuitry is also included for idling a selected one of the left and right paths of mixer 115 when selected data path to mixer 115 is muted.

Abstract: A content addressable memory cell 920 includes a first storage element 922a for storing information and a first transistor 921a for selectively transferring charge representing information from a first bitline 924a to the first storage element 922a. A second transistor 921b selectively transfers charge representing information from a second bitline 924b to a second storage element 922b. First and second comparelines 925a, 925b carry first and second bits of a comparand to a comparator 905, 906, 908 which compares the first and second bits of the comparand with information stored on the first and second storage elements. In response, comparator 905, 906, 908 selectively controls a voltage on a corresponding one of a plurality of matchline 909.

Abstract: Imager rejection circuitry includes a first digital path including a finite impulse response filter 202 having a variable gain stage 204 operable to apply a gain to a first digital signal in response to a coefficient selected from a coefficient table 206 and an adder 205 for summing the first digital signal to the output of the variable gain stage 205 to produce a corrected first digital signal. A second digital path processes a second digital signal and error calculation circuitry 207 determines an error between the first and second signals for selecting a coefficient from the coefficient table 206.

Abstract: A continuously variable color display system includes a plurality of display areas, each including three light emitting diodes, for emitting light signals of respectively different primary colors, which are controlled by three bistable devices, respectively. Each bistable device is set at the beginning of a time interval, defined by a corresponding input digital code, and reset at the end of the time interval. Accordingly, the light emitting diodes jointly illuminate in a composite color determined by three input digital codes.