Abstract: A digital to analog converter re-codes a stream of 1-bit digital data into a stream of multiple-bit data with a gain greater than one. The resulting stream of multiple-bit data is then converted into analog form in a multiple-bit digital to analog converter. By applying a gain of greater than one to the 1-digital data stream the higher modulation index available in the multiple-bit can be exploited.

Abstract: A method and a device for supplying powder to a scattering device, comprising a device for producing negative pressure, a device for producing excess pressure, a powder container for receiving a powder reserve, and a separating device which is located inside the powder container and which separates a quantity of the powder reserve from the remainder in the powder container. The excess pressure device is connected to an air supply device. When the excess pressure device allows the air to strike the quantity of powder which has been separated, the powder forms swirls. The negative pressure device is connected to the powder container in such a way that the swirling powder is conveyed out of the powder container and to the scattering device by the negative pressure.

Abstract: A bracket 107 for retaining a stair rod 106 includes a first portion 301b for affixing to a stair including means 304 for securing a finial thereto and a seat 301/302 for receiving an end of the corresponding stair rod 106. A second portion 301b is rotatably coupled to the first portion 301a and includes means for retaining the end of corresponding stair rod 106 in the seat of the first portion 301a of bracket 107. Means 402 are also provided for holding the first and second portions of the bracket in engagement.

Abstract: A user customizable pendant that includes a frame with a hole, a transparent front window, and a back member, which may or may not also be transparent. The front window and back member couple to the frame to form a vessel with an inner cavity. The pendant includes a funnel coupled to the frame, with a hole at the bottom that provides access to the inner cavity ofthe pendant. The user customizes the pendant by placing real or simulated birthstones, other simulated stones, charms, or other small objects into the inner cavity through the funnel such that they are visible through the front window. In one embodiment, the funnel includes two aligned, transverse holes, through which a necklace, bracelet, chain, cord, ribbon, or other structure can be threaded that captures the objects inside the pendant. In another embodiment, the funnel is located at the side, and the pendant may or may not include a plug capable of being removably coupled to the funnel to block the bottom hole.

Abstract: A voltage out-of-calibration detector 200 includes a voltage divider operating between first and second voltage rails and having a plurality of taps 203 for generating first and second comparison voltages. A first set of switches 205 selectively couples at least one of the plurality of taps 203 to the input of a first voltage comparator 401a, first voltage comparator 401a comparing the first comparison voltage with an input voltage and outputing a signal when the input voltage exceeds the first comparison voltage. A second set of switches 206 selectively couples at least one of the plurality of taps 203 to an input of a second voltage comparator 401b, second voltage comparator 401b comparing the second comparison voltage with the input voltage and outputing a signal when the input voltage is below the second comparison voltage. Control logic 300 selectively activates the first and second sets of switches 205/206 in response to received control signals.

Abstract: An audio system 100 includes digital-to-analog converters 110 having left and right paths for converting received left and right streams of digital audio data and a plurality of analog data ports for receiving left and right channel streams of analog audio data. Mixer 115 has left and right paths for selectively mixing left and right channel data passed from converters 110 and left and right channel data passed from the analog data ports. Muting circuitry is also provided for selectively muting said right and left channel data to be passed to mixer 115 from converters 110. Circuitry is also included for idling a selected one of the left and right paths of mixer 115 when selected data path to mixer 115 is muted.

Abstract: A method for continuously controlling color of a display device comprises the steps of receiving three sets of data respectively representing the portions of three primary colors, accumulating three counts in accordance with the data, respectively, and setting three bistable devices for the respective durations of the accumulating. The outputs of the three bistable devices are coupled for respectively energizing three buses, to which the light emitting diodes of three primary colors are connected in accordance with their colors, for controlling the portions of the light signals of the primary colors emitted therefrom.

Abstract: A content addressable memory cell 920 includes a first storage element 922a for storing information and a first transistor 921a for selectively transferring charge representing information from a first bitline 924a to the first storage element 922a. A second transistor 921b selectively transfers charge representing information from a second bitline 924b to a second storage element 922b. First and second comparelines 925a, 925b carry first and second bits of a comparand to a comparator 905, 906, 908 which compares the first and second bits of the comparand with information stored on the first and second storage elements. In response, comparator 905, 906, 908 selectively controls a voltage on a corresponding one of a plurality of matchline 909.

Abstract: Imager rejection circuitry includes a first digital path including a finite impulse response filter 202 having a variable gain stage 204 operable to apply a gain to a first digital signal in response to a coefficient selected from a coefficient table 206 and an adder 205 for summing the first digital signal to the output of the variable gain stage 205 to produce a corrected first digital signal. A second digital path processes a second digital signal and error calculation circuitry 207 determines an error between the first and second signals for selecting a coefficient from the coefficient table 206.

Abstract: An audio system 100 disposed on a single chip includes an output mixer 115 having inputs for receiving first digital audio data of a first bit width from a first digital-to-analog converter 110, digital audio data of a second bit width from a second digital-to-analog converter 6601, and analog data from an external port. An output port drives an analog signal output from the output mixer. An input mixer 114 has inputs for receiving analog data from a plurality of sources and analog-to-digital converters 111 to convert an analog output from the input mixer into digital data. An input path transmits the digital data output from the analog to digital convertors 111 to an external digital bus.

Abstract: A continuously variable color display system includes a plurality of display areas, each including three light emitting diodes, for emitting light signals of respectively different primary colors, which are controlled by three bistable devices, respectively. Each bistable device is set at the beginning of a time interval, defined by a corresponding input digital code, and reset at the end of the time interval. Accordingly, the light emitting diodes jointly illuminate in a composite color determined by three input digital codes.

Abstract: A variable color light emitting diode digital display system automatically exhibits integers and decimal numbers in different colors. A logic circuit is provided for detecting the presence or absence of a decimal point in a string of digits. The color of the exhibited digits is controlled in accordance with the detection.

Abstract: A memory 200 comprises a first memory bank 201a including an array of memory cells 202a and row and column address circuitry 203a, 205a for addressing a location within the array 202a. The memory further includes a second memory bank 201b including an array of memory cells 202b and row and column address circuitry 203b, 205b for addressing locations within the array 202b. Row and address column circuitry 203, 206, 207 is included for selectively pipelining a plurality of serially received words of address bits to the banks. Furthermore, circuitry places the memory into priority precharge in response to a priority signal, where the priority precharge terminates a current access to the memory and some addresses required for a priority access are selectively pipelined during priority precharge.

Abstract: Memory 200 having an array of rows and columns of memory cells, each column associated with a pair of complementary bitlines 302a, 302b. An access sense amplifier 203 coupled to each pair of complementary bitlines 302a, 302b for sensing and latching data from cells along a selected row during a first portion of a random access cycle. Refresh sense amplifier 204 is coupled to each pair of complementary bitlines for 302a, 302b for refreshing data from cells along a selected row during a second portion of the random access cycle.

Abstract: An automated third party verification system and method for verifying a customer's authorization to switch long distance service providers. The system broadly comprises a customer database manager, a third party verification (TPV) interactive voice response (IVR) system, and a TPV management system. The customer database manager contacts the customer and, responsive to the customer's authorization to switch long distance carriers, creates a text file of the customer's responses to a series of questions supporting the authorization. The text file is sent to the TPV IVR system. The TPV IVR system directs a series of scripted questions, corresponding to those already asked by the customer database manager, to the customer and records the responses as voice clips. The TPV management system presents the voice clips and the corresponding text file to a verifier through a voice data verification module.

Abstract: A cover 30 for a selected dental hand piece 10 includes a body 32 having first and second halves 34a, 34b of a shape and dimensions selected to substantially conform with a shape and dimensions of selected hand piece 10, said halves. Hinge 36 couples the first and second halves 34a, 34b of body 32 for allowing the first half 34a to rotate with respect to the second half 34b to thereby form an enclosure for enclosing a substantial portion of hand piece 10. The enclosure includes a head portion 42, handle portion 32 and a substantially rigid neck portion 40 between handle portion 32 and head portion 42.

Abstract: A current mirror 100 includes a current mirroring transistor 103 having a selected aspect ratio for conducting a mirrored current of a selected mirroring ratio with respect to a reference current. A plurality of reference current transistors 201 are disposed in parallel with current mirroring transistor 103, each of the reference current transistors 201 having a current path coupled to a source 105 of the reference current and a selected aspect ratio. A switch 207 is coupled to a control terminal of a selected reference current transistor 201a, for selectively turning on and turning off a selected reference current transistor 201a to adjust the mirroring ratio.

Abstract: Audio data processing circuitry 300 includes a plurality of analog inputs 101 for receiving analog audio data and a digital input 105 for receiving digital audio data. A analog mixer 312 mixes analog data received at said plurality of analog inputs 101 to generate a mixed analog audio stream. An analog-to-digital converter 313 converts the mixed analog audio stream to a digital audio stream and a digital mixer 315 mixes digital data received at the digital input 105 with the digital audio stream from the analog mixer 312 to generate a mixed digital audio stream.

Abstract: A digital to analog converter 102 receives a data stream at a first over-sampling rate and quantizes a second data stream derived from that stream at a second, higher oversampling rate for reducing out-of-band quantization noise in an analog output of the digital to analog converter.

Abstract: A memory 1300 including an array of rows and columns of memory cells 501 is disclosed. For each column, first and second interdigitated bitlines 1301, 1303 are coupled to the cells of the column. The first bitlines 1301 has an end coupled to a sense amplifier 1302 at a first boundary of the array and a second bitline 1303 has an end coupled to a second sense amplifier at a second boundary of the array, the first and second boundaries being spaced apart by the array. Control circuitry 508 precharges the first bitlines 1301 of the columns of the array substantially simultaneous to an access to the array through the second bitlines 1303 of selected columns of the array.