Abstract: Sensing circuitry including a sense amplifier 400 for latching a bit of data on a true bit line and a complementary bit of data on a complementary bit line. Circuitry 403, 404, 405 is included for performing boolean operations on bit of data latched in sense amplifier 400 in response to a bit of modifying data. Circuitry 403, 404, 405 during an AND operation pulls down the true bit line when the bit of modifying data a logic 0.

Abstract: A step generator 800 including at least one gate 805 and a voltage divider 806 coupled to an output of gate 805. The selected node of voltage divider 806 provides an output V.sub.OUT of generator 800. Circuitry 801 presents a signal to an input of gate 805 to initiate current flow through voltage divider 806.

Abstract: A memory 20 includes a first array 100 and a second array 102 of memory cells. A first data port 118 allows for the exchange of data with the first array 100 and a second data port 120 allows for the exchange of data with the second array 102. Memory system 20 also includes a circuitry 122 for controlling data exchanges in a selected mode with the first array 100 via the first data port 118 and with the second array 102 via the second data port 120, the exchanges with the first and second arrays 100 and 102 being asynchronous.

Abstract: A memory 600 including an array of memory cells 201 and a plurality of input/output terminals 220 for receiving control bits during control cycles and accessing selected ones of the cells 201 during data access cycles. A command bit input terminal 221 is provided for receiving command bits for initiating the control cycles and a mapping input terminal 222 is provided for receiving a mapping enable signal to initiate a mapping mode. Circuitry 215/ 216 is provided for decoding control bits received during at least one control cycle occurring during a mapping mode for allowing a mapping of a set of addresses for accessing the cells of the array 201.

Abstract: A memory including a plurality of input/output terminals 220 for exchanging data bits during a data access cycle and receiving command and control bits during a command and control cycle. The memory further includes an array of memory cells 201, a data input/output circuitry for transferring data between the input/output terminals and the array of memory cells during the data access cycle, and control circuitry for controlling operations of the memory in response to command and control bits received at the input/output terminals during the command and control cycle.

Abstract: A memory comprising a first memory bank 201 and a second memory bank 201 includes a plurality of data input/output terminals, a first subset of the plurality of data input/output terminals for accessing the first memory bank and a second subset of the plurality of data input/output terminals for accessing the second memory bank.

Abstract: A computer graphics display system and method are described for rendering objects formed of at least one geometric primitive as pixel images which collide or intersect in three dimensional space. A depth buffer stores depth information representing graphics images rendered by the graphics system. Data stored in the depth buffer representing graphics objects displayed in the three dimensional space are partitioned into three portions comprising an identification portion to store information identifying each object rendered in the three dimensional space, an object resolution portion to store data for controlling the resolution of the graphics object on a display screen, and a depth coordinate portion for storing the coordination information of the object rendered in the three dimensional space. A collision detection is provided to detect and determine when two objects collide on the display screen.

Abstract: A method is disclosed for controlling tearing in a display control system which includes first and second buffers, with input of data to a selected one of the buffers controlled by an input pointer and output of data from a selected one of the buffers controlled by an output pointer. Data is first input into the first buffer and substantially simultaneously data is output from the first buffer. The output pointer is then toggled such that data is input into the first buffer and output from the second buffer. Next, the input pointer is toggled, such that it is input into the second buffer and data is output from the second buffer. The output pointer is again toggled such that data is output from the first buffer and input into the second buffer.

Abstract: A system 500 is provided for transferring signals across a bus which includes a power source 550 operating between a high voltage rail at a first supply voltage level and a low voltage rail at a second supply voltage rail, power source 550 generating a third supply voltage level on an output thereto. The third supply voltage level is greater than the first supply voltage level. A processing circuitry 103, 104 is included for generating a plurality of data signals each having a first voltage swing between a first logic high level substantially equal to the first supply voltage level and a first logic low level substantially equal to the second supply voltage level. The system additionally includes a plurality of buffers, 520, each buffer 520 being coupled to the power source 550 output and receiving a selected one of the data signals.

Abstract: A memory subsystem with multiple memory banks each having an array of memory cells includes address control circuitry for presenting address bits to the row and column decoders of the memory banks and switching the row and column addresses presented to the different banks. Address control circuitry may be a translation look ahead buffer or may include an address translator, a row address buffer, and a column address buffer. The memory subsystem may also include input/output circuitry for inputting address bits in response to row address strobe and column address strobe signals. Input/output circuitry may allow both serial and parallel access to the multiple memory banks.

Abstract: A memory system 104 is provided which includes an array 200 of memory cells arranged in rows and columns. Circuitry 207, 208, 209, 210 is also provided for selectively performing logic operations on a bit of data stored in a selected memory cell using a bit of received modifying data. Circuitry 207, 208, 209, 210 for performing logic operations is operable during an AND operation to write the bit of modifying data into the selected memory cell when the bit of modifying data is a logic zero and maintains an existing bit stored in the selected cell when the bit of modifying data is a logic one.

Abstract: Within a data processing system, data transfer between a host device and a slave device is accomplished with only one write operation. The write operation performed by the host device, such as a central processing unit, is performed to an alias destination address, which is related to the destination address by an offset number. The data included within the write operation includes the source address of the data to be transferred. Such a data transfer operation could be utilized to transfer data to a display adapter for display of video related data on a display device.

Abstract: A memory subsystem 300 including processing circuitry 103 and first and second banks of memory 200/201. Each bank 200/201 includes a predetermined number of primary memory cells 200 and a predetermined number of redundant memory cells 205. An address bus 202 allows processing circuitry 103 to address at least one of the primary cells 200. The redundancy bus 301 allows processing circuitry 103 to address at least one of the redundancy cells 205.

Abstract: A memory 20 is disclosed including a first column of memory cells including a conductive bitline 202 and a second column of memory cells also including a conductive bitline 202. A gate 203 is provided for selectively coupling the bitline 202 of the first column with the bitline 202 of the second column for transferring a bit of data from a selected cell of the first column to a selected cell of the second column.