Abstract: Memory 900 includes an array 401 of rows and columns of memory cells, each row associated with first and second wordlines and each column associated with first and second bitlines. A first port (PORT1) is utilized for accessing selected ones of the memory cells using the first wordline and the first bitline of corresponding ones of the rows and columns, first port (PORT1) associated with first dedicated sets of address, data, clock and control signal terminals for supporting accesses via first processing device 101 using a time base and an access-type required by such first processing device. A second port (PORT2) is utilized for accessing selected ones of the memory cells using the second wordline and the second bitline of corresponding ones of the rows and columns, second port (PORT2) associated with second dedicated sets of address, data, clock and control signal terminals for supporting access by a second processing device 1002.

Abstract: A method of processing a stream of audio information received by a multiple processor audio decoder. Processing operations are performed by a first processor on the stream of audio information to produce at set of results. The first processor writes the set of results into a shared memory and a flag is set indicating that the results are ready. In response to the flag, a second processor reads the results from shared memory. When the results have been read from shared memory, the second processor sends a command to the first processor. The first processor then clears the flag.

Abstract: An improved method and apparatus for anchoring tensioning members in a concrete structure and the like wherein there is provided a wedge support member having wedge-receiving pockets coaxially aligned with the anchor seats in an anchorage block permitting the anchorage wedges to first be inserted into the pockets not allowing the tensioning members to slip during tensioning. This method is used in post-tensioning of monostrand cable. The apparatus anchors the tensioning members by installing wedges into their respective wedge seats. A magnetic tip is utilized to hold the wedges in place while a slide hammer provides and transmits the energy to forcibly insert the wedges.

Abstract: An optic sensor for use in a well is provided. The sensor can be configured to sense downhole conditions, such as temperature, pressure, or stress, either individually or in combination. The optic sensor has a sensor housing that defines a chamber. The sensor housing also defines a region that is responsive to an external force. An optic fiber extends through the housing. The optic fiber has a dielectric boundary that resides within the housing chamber , and has a refractive index variation that provides maximum reflectivity at a central reflectivity wavelength, the central reflectivity wavelength correspondingly shifting with respect to an expansion or contraction of the region. In a further aspect of the invention, the optic fiber has a second dielectric boundary spaced apart from the first dielectric boundary.

Abstract: A memory 700 having an array 701 of rows and columns of dynamic memory cells 301, cells 301 of each row coupled to a refresh wordline 303a and an access wordline 303b and cells 301 of each column coupled to a refresh bitline 302a and an access bitline 302b. Refresh circuitry 711, 712, refreshes selected rows of cells corresponding to a refresh wordline 303a and a corresponding one refresh bitline 302a. Access circuitry accesses selected cells of a selected row using corresponding access wordline 303b and corresponding one of the access bitlines 302b. The access circuitry includes a new address detector of 709 for detecting receipt of a new address of said memory, a row decoder 702 for selecting access wordline in response to receipt of the new address and access sense amplifiers 703 and an access column decoder 704 accesses at least one cell along the selected wordline 303b using the corresponding access bitline 302b.

Abstract: A dynamic random access memory 400 includes an array 401 of physical rows and columns of memory cells, the cells of each row coupled to first and second wordlines 603 and first and second bitlines 602. A direct input/output data path 402 having a width equal to a width of the rows supports simultaneous writing to each of the cells along a selected row using the first wordlines and first bitlines during a single access cycle without restore.

Abstract: A data processing system having a DRAM and a non-volatile memory, such as a ROM or a programmable ROM (PROM), is implemented on a single integrated circuit using DRAM data processing techniques. The DRAM is manufactured in accordance with known processing techniques. The non-volatile memory is manufactured using the same DRAM manufacturing techniques, with the addition of a processing step in which a first terminal of a stacked capacitor manufactured in accordance with the DRAM process, is coupled to a known-reference voltage. This stacked capacitor structure may be coupled to a known conductor through the formation of a via and the subsequent coupling of a conductor to the stacked capacitor structure through the via. Alternatively, the stacked capacitor structure may be coupled to the known reference voltage through an internal connection to that reference voltage.

Abstract: A method of automatically detecting a data format type of a stream of data. A determination is made as to whether a current word and a previously received words comprise a set of identifiers associated with a selected type of data. When a preselected number of detections of the set of identifiers has been reached within a predefined time period, the input stream is declared to be the selected type of data. Simultaneously, when the selected type of data is not detected, other data types are sequentially selected for similar checking. This successive selection of different data types allows the method to classify the input data into one out of multiple data types.

Abstract: Analog modulator circuitry 401 includes an integrator 707. First switched capacitor circuitry 710, 711, 713, 714 selectively samples a first amount of charge from a feedback signal and couples that first amount of charge to the first and second inputs of the integrator. Second switched capacitor circuitry 711, 714, 716, 717 selectively samples a second amount of charge from the feedback signal and couples that second amount of charge to the first and second inputs of the integrator stage to selectively compensate for an offset of an input signal to the integrator with respect to a reference voltage.

Abstract: A tape feeder 200 includes a sprocket 201 having a plurality of teeth 202 for engaging holes of a tape. A pawl 205 engages selected teeth of sprocket 201. A first lever 203 is coupled to pawl 205 and a second lever 204 is coupled to first lever 203 and a source 208 of a driving force. First lever 203 and second lever 204 operate by a toggle action to selectively engage pawl 205 with ones of teeth 202 and thereby index sprocket 201.

Abstract: A multiprocessor processing 200 includes a memory system having a memory controller 202 for linking a plurality of processors 201 with an integrated memory 203. Integrated memory 203 comprises a plurality of static random access arrays 603 and a dynamic random access 407.

Abstract: An optical memory 200 including an optical storage element 301 for storing data as a packet of photons, optical storage element 301 delaying in time the packet of photons traveling through the storage element from a first point to a second point. A photon source 302 receives an electrical signal representing data and injects the packet on to optical storage element 301 in response, and a detector 303 selectively detects the packet traveling on optical storage element 301. A feedback path 306/305 couples photon source 302 and detector 303 for recirculating the packet through storage element 301.

Abstract: The method of mounting a semiconductor device 200 on a supporting structure 101, the semiconductor device having a surface 201 including a defined area 202 for receiving photons and a plurality of conductors 203/204 for establishing connections to the device. An aperture 301 is formed through the supporting structure, the aperture sized to correspond to a size of the defined area of the semiconductor device. Conductors 302 are formed on the supporting structure adjacent to the aperture in a pattern corresponding to the pattern of the conductors on the semiconductor device. The semiconductor device is mounted to the supporting structure such that the conductors on the semiconductor device contact the conductors on the supporting structure where the defined area of the semiconductor device is exposed to photons through the aperture.

Abstract: A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325. The system CPU initiates data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the graphics engine 325. In an alternate embodiment, the subsystem includes a subsystem master control unit or MCU to enable parallel or simultaneous operation of the Host XY unit and the graphics subsystem MCU.

Abstract: Display control circuitry is provided which includes a frame buffer 104 having a plurality of memory spaces 301 each for storing a block of display data. Circuitry 200 is provided for generating display position data representing a position on a display screen corresponding to a current display pixel being generated. For each memory space 301, a window control circuit 201 is provided for controlling the transfer of a block of data from the given memory space 301 to a selected window on the display screen. Each window control circuit 201 includes first registers 205, 206 for storing data defining horizontal boundaries of the window, second registers 210, 211 for storing data defining vertical boundaries of the window, and circuitry 207, 208, 209, 212, 213, 214 for comparing the display position data with data stored in the first and second registers and generate an enable signal when the position on the screen of the current pixel is within the window boundaries.

Abstract: A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a message is written into a second register with the first processor. The pending flag is set to a second selected logic state with the first processor and an interrupt to the second processor is generated. The message is read from the second register with the second processor when the pending flag is in the second logic state. The pending flag set to the first logic state with the second processor.

Abstract: A processing system 100 is provided which includes processing circuitry 103 fabricated on an integrated circuit chip 107. An internal memory 104a is also fabricated on chip 107. A first first-in/first-out memory 201 is provided having an input for receiving data retrieved from the internal memory 104a and an output for providing data to processing circuitry 103. An external memory 104b is provided. A second first-in/first-out memory 202 includes an input for receiving data retrieved from the external memory 104a and an output for providing data to the processing circuitry 103.

Abstract: A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.

Abstract: An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

Abstract: An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface 403. The system also includes a master processing device which is operable to write at least some bits of a starting address into bus interface 403, determine an ending address for subsystem 402 and lock subsystem 402.