Abstract: A computer cabinet and hot-pluggable disk drive module design including indicator light support for the disk drive module. The cabinet includes a disk drive module receiving bay into which the disk drive module is removably installed. The disk drive receiving bay includes a backplane having at least one connector for engagement with a corresponding connector, preferably a single connector architecture (SCA) connector, protruding from a leading surface of the disk drive module. A light source mounted to the backplane near the backplane connector is illuminated to provide status information concerning the disk drive module. A light conduit extends from the light source to a conspicuous viewing location on the computer cabinet. Multiple indicator lights and corresponding light conduits tinted to different colors may be employed to provide different status indications, e.g., power, activity and fault status information.

Abstract: High pressure jackscrew connectors for removably attaching a first component to a second component having an internally threaded member. One preferred embodiment described includes a panel mount member which is attached to the first component to be joined. When attached to the first component, the panel mount member retains an internally threaded ejector member. A pressure inserter member having a longitudinally extending externally threaded portion engages with the internal threads of the ejector member and the internal threaded member of the second component to pull the ejector member towards the pressure inserter member and push the first component towards the second component upon rotation of the pressure inserter member.

Abstract: A mechanism for distributing interrupts to processors within a multi-processing system including a cache memory corresponding to each processor, a main memory, a bus structure connecting the processors and their associated cache memories with the main memory, and a cache coherency mechanism to maintain data consistency between the cache memories and the main memory. An address within the main memory is assigned to each processor within the system, the assigned address being associated with an interrupt for the processor to which it is assigned. For each processor, a copy of the contents of its assigned address is thereafter read into its corresponding cache memory. Thereafter when a cache coherency operation to update the contents or status of the cache memory address occurs, a comparison is made between the cache memory address presented to the cache memory through the system bus structure and a stored interrupt base address.

Abstract: A Plug-and-Play (PnP) configuration driver initilization routine and PnP configuration utility for use in PCI bus architectures supporting dynamic I/O bus configurations. The PnP configuration driver includes a logical-to-physical PCI bus mapping scheme maintaining a PCI bus mapping table, and creating a logical-to-physical map table at start-of-day. PCI device drivers access devices through the logical bus numbers, thereby avoiding errors resulting when physical bus numbers change as a result of the addition or removal of buses within a computer system supporting dynamic I/O bus configurations.

Abstract: An image based, dual path, document processing system including an imaging unit, a character recognition unit, a dual path module and an encoder. A document received by the system is sequentially processed through the imaging unit, the character recognition unit, the dual path module and the encoder. The imaging unit images the front face of the document and attempts to identify character data appearing on the face of said document, such as a hand-written courtesy amount appearing on a bank check, while the character recognition unit is utilized to reads machine-readable data, such as MICR data, printed on the face of the document.

Abstract: A method for identifying and repairing file system damage following the failure of a processing node within a clustered UNIX file system including a plurality of processing nodes, an interconnection network connecting the processing nodes, and a data storage device connected via a shared interconnect with each one of the plurality of processing nodes. The method includes the step of maintaining a journal for each processing node, each journal containing a bit map identifying inodes to which its associated processing node has acquired and retains an exclusive right. Each bit map journal is updated whenever its associated processing node acquires an exclusive right to an inode. Following a failure of a processing node, a non-failed processing node is designated to audit the inodes associated with the failed node. Auditing is accomplished by reading the bit map journal associated with the failed processing node and obtaining the exclusive right to every inode found within the journal.

Abstract: A mechanism for ensuring coherency between a system memory and a cache memory within a processing system including a first split transaction bus, the system memory being connected to the first split transaction bus; a second split transaction bus; a bus agent including the cache memory connected to the second split transaction bus, and a bus interface unit connecting the first and second split transaction busses for transferring bus cycles between the first and second split-transaction busses. The mechanism records bus cycles, such as read cycles, write cycles and cache line invalidate cycles, directed from the first split transaction bus to the second split transaction bus into a transaction queue within the bus interface unit, and sequentially transfers these cycles to the second split transaction bus in the order in which these cycles are recorded into the queue.

Abstract: A datagram messaging service for a distributed lock manager implemented on a clustered computer system including a plurality of processing nodes interconnected through a network. The messaging service establishes and maintains a plurality of virtual circuits between the processing nodes, a single virtual circuit connecting each pair of processing nodes within the clustered computer system. A distributed lock manager driver is included within each processing node, the driver including a communication service providing for the generation of datagrams comprising lock manager instructions for transmission to other processing nodes within the clustered computer system via said virtual circuits and also providing for the receipt of datagrams generated and transmitted by the other processing nodes.

Abstract: A split-range address detector and translator for interfacing a system processor with a memory array. The split-range detector generates a select signal for the memory array whenever an input address received from the system processor resides in either of two, non-contiguous, address ranges. The split-range detector includes a first range detector which generates a first range detection signal when the address received from the system processor is within a first, lower, range of addresses, and a second range detector which generates a second range detection signal when the input address is within a second, upper, range of addresses. The output signals are combined together to produce the select signal for the memory array. The address ranges are defined by upper and lower address limits stored within programmable registers.

Abstract: A method for displaying status information during execution of an application task in a windowed application. The method provides two formats for displaying status information for an application task: (1) a detailed display format wherein status information is presented in a dialog box displayed over the application window, obscuring a portion of the application window, and which remains displayed until execution of the application task completes and obscuring a portion of said display screen; and (2) a concise display format wherein a brief summary of the status information is presented in a message displayed in a status bar along the bottom edge of the application window. The detailed display format wherein status information is presented in a dialog box is presented as the default display format. The concise display format is selected by dragging the title bar for the dialog box into the status bar, the concise display format thereafter being displayed in substitution for the detailed display format.

Abstract: A procedure for scheduling multiple process requests for read/write access to a disk memory device within a computer system. The procedure considers disk characteristics, such as the number of sectors per track, the number of tracks per cylinder, speed of disk rotation and disk controller queuing capability in determining the optimal order for executing process requests. Process requests are placed in packets within an execution queue, each packet including up to a predetermined maximum number of requests. Within the packets, the process requests are sorted in ascending/descending order by the cylinder number to which the requests desire access, while within each cylinder the requests are placed in next-closest-in-time sequence.

Abstract: A method whereby a host computer system is informed of the drive status in a disk array when one or more of the disk drives fail. A data pattern (timestamp or status code) is written on each of the disk drives in service in the array when an event occurs which changes the operating state of an array. The state of an array changes only when the array is configured, unconfigured, a disk drive fails, parity is marked inconsistent or the array is restored. The timestamp includes a binary number to allow the system to determine the status of each disk drive in the array. At each state, the timestamp on each of the operating disk drives is updated to reflect the number of operating disk drives and the status of the parity data. The distinct binary numbers that result when the array changes states allow the system to maintain the data integrity of the array.

Abstract: A high performance scaleable hardware architecture for a disk array storage subsystem which supports RAID modes 0, 3, 4 and 5. The architecture features a high bandwidth parity calculation engine, a buffered PCI interface operating at the full speed of the PCI bus, and a dedicated local memory. The dedicated local memory is dual ported so that PCI and parity operations may operate concurrently. The architecture of the disk array controller allows parity calculations and memory block moves to occur without interfering with the controller processor or its associated memory, freeing the controller processor to manage array task control. The array controller configuration allows simultaneous operation of data block moves between storage I/O devices and local memory; data block moves between host SCSI connections and local memory; parity calculations; and normal CPU memory fetches, queued operations for block moves and queued operations for parity tasks.

Abstract: A Video-On-Demand (VOD) system including a plurality of video storage devices; an asynchronous transfer mode (ATM) telephony technology network connected to provide video data to a plurality of subscribers; and a unique video server coordinating the conversion and transfer of video data from computer technology devices to the ATM telephony technology network.

Abstract: A method for redistributing the mastership of system resources among the processing nodes within the clustered computer system following a change in the system configuration, such as the failure of a processing node or the return to service of a failed processing node. The method includes the steps of: maintaining a set of hash buckets within each processing node; assigning each one of the resources to one of the hash buckets; and assigning a hash vector, determined through utilization of an N-way recursive algorithm, to each one of the hash buckets, each one of the hash vectors identifying the processing nodes within the clustered computer system in a predetermined sequence unique to the one of the hash buckets. Mastership of any system resource resides with the first processing node identified by the hash vector assigned to the hash bucket to which the system resource is assigned.

Abstract: A wireless radio local area network is provided including a host station and one or more remote stations. When a diagnostic link is established between two stations in the network, diagnostic information with respect to the integrity of the link is collected. Each of the network stations engaging in diagnostic activity transmits a special diagnostic frame including a diagnostic network identification designator (NWID) code to the other stations in the network. For example, the host station transmits a diagnostic frame including the diagnostic NWID code. The host station then listens for other remote stations with the same diagnostic NWID code to transmit their diagnostic frames. The host station, which is the receiving station in this example, is capable of determining if any of the received diagnostic frames from the other remote stations exhibit the same diagnostic NWID code as the host station.

Abstract: A scalable software architecture, for optimal performance on a RAID level 1, 3, 4 and 5 disk array or tape array. The software architecture consists of a software device driver and one or more driver daemon processes to control I/O requests to the arrays. Implemented in a UNIX or NetWare operating environment, this architecture provides a transparent interface to the kernels I/O subsystem, physical device drivers and system applications. The array driver and I/O daemon can be run on a uni-processor or multi-processor system platform to optimize job control, error recovery, data recreation, parity generation and asynchronous writes.

Abstract: A transfer memory backup system for a RAID level 5 disk array storage system which includes a transfer buffer, wherein write data received by the array is written into a transfer buffer, and a write complete status signal generated, prior to the write data being written to the disk drives within the array. The transfer memory backup system includes a low power, industry standard PCMCIA (Personal Computer Memory Card International Association) device along with a small, temporary voltage source made up of a small rechargeable battery or a high capacitance gold capacitor. Upon the detection of a disk array storage system failure, low power logic provides continuous refresh for the transfer buffer as well as power to the components included in the transfer memory backup system upon a disk array storage system failure. A low power CMOS microprocessor with self contained microcode (mask programmable ROM) controls the transfer of data from the transfer buffer to removable storage medium within the PCMCIA device.