Abstract: A local area network system includes a wired backbone LAN (12) and at least one wireless LAN (14) cooperating with the backbone LAN (12) via an access point (22), which has a bridging function. When a source station (30) in the wireless LAN (14) transmits a packet to another station in the wireless LAN (14), the destination station should respond with an ACK signal. If no ACK signal is received by the source station, the packet is retransmitted. The access point (22) also receives the transmitted packet and if the access point (22) does not detect an ACK signal on the wireless channel', the access point (22) itself generates an ACK signal and retransmits the packet on the wireless LAN (14) or forwards the packet to the wired LAN (12) according to the packet destination address.

Abstract: A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique four-bit Micro Channel arbitration values assigned to the bus masters to retrieve buffer configuration parameters stored within a register file containing different configuration parameters for each bus master. The data buffer is dynamically configured for optimal performance with each bus master having control of the Micro Channel bus in accordance with the parameter data retrieved from the register file.

Abstract: A diagnostic system for a large, multiple processor data processing system. Diagnostic access between dual diagnostic intelligent consoles and each processor is provided through a diagnostic network of communication links and switching nodes which are independent of normal data processing system communication channels. The diagnostic network consists of two embedded three structure communication networks providing two different diagnostic communication paths to each processor within the data processing system.

Abstract: An apparatus for extending the memory of an electronic data processing system and a method for providing access to the extended memory for reading data, writing data, and refreshing data. The method provides a partitioning of the original virtual address space into a reduced virtual address space and an extended real memory address space. An extended address register is loaded initially with an extended memory control word by the operating system, but this word may not be changed again until the current process is over. If this control word is changed, it is changed by the operating system such that the use of the extended memory is transparent to the application processes using the system. The method further provides for refreshing of the memory circuitry of the extended memory. The apparatus supports the extended real memory address space by decoding the read and write accesses to the extended real address space, and by providing electrical connections for the refreshing of the extended memory circuitry.

Abstract: A system and method for providing power from a source of stored electrical energy to a microcomputer for a user established "ride-through" period of time after a disruption in the primary power supply for the microcomputer. If the primary power supply is not restored within the ride-through time period the system performs an orderly shut down of computer applications. Should stored energy reserves run low during the primary power disruption, the system instead performs an abbreviated, critical application shut down. Following application shut down, or upon the expiration of a user established "shut down" time period, the system performs an orderly shut down of computer system operations and thereafter removes all power from the computer. Shut down and shut off procedures are canceled, if possible, upon restoration of the primary power supply.

Abstract: A multi-chip module board includes a multi-chip module substrate; a first multi-chip module designed and assembled into the substrate; and a space on the substrate configured to receive an additional add-on multi-chip module, memory module or component module and to operatively connect the add-on module to the first multi-chip module. The first multi-chip module contains integrated and discrete circuit elements necessary to provide basic functionality required by the board user. Space and connecting structure is provided on the module board for the connection of add-on modules which provide additional or peripheral functionality to the board. The connecting structures included on the module board and the add-on modules are designed to permit the attachment of any one of several different function add-on modules to a location on the module board.

Abstract: A vision processing apparatus and method for detecting and monitoring traffic flow. The method includes the steps of generating successive images of a section of roadway; transducing the successive images into successive arrays of pixels, each pixel having a luminance value associated therewith; summing the luminance values of all pixels contained within a subarray, or "window" in each one of the arrays; comparing the pixel luminance sum for each one of the subarrays to a reference value; and generating data indicative of the presence of traffic in the section of the path when the difference between the pixel luminance sum and the reference value exceeds a predetermined value. The generated data can thereafter be analyzed to determine various traffic and vehicle parameters, or can be used to operate traffic control devices.

Abstract: An array controller including a novel data path structure for effecting data transfers between a host computer system bus and four array busses associated with a RAID level 3 disk array without the utilization of a buffer between the host system and the array. The data path structure includes a host register associated with each array bus, each host register being connected to the host bus for receiving data therefrom; a first array register associated with each array bus, each first array register being connected to a corresponding host register for receiving data therefrom and connected to its associated array bus for providing data thereto; and a second array register associated with each array bus, each second array register being connected to it associated array bus for receiving data therefrom and connected to the host bus for providing data thereto.

Abstract: A fast centralized arbitrator for avoiding contention between up to eight processors or other smart devices having access to a shared computer facility. Each of the processors or smart devices is assigned a unique three digit octal formatted priority level. A first set of 1-of-8 decoders, AND gates and a prioritizer circuit are employed to determine the priority level of the highest priority device requesting access to the shared facility. A second set of 1-of-8 decoders, each having associated therewith a set of OR gates for combining the decoder outputs with the outputs of the prioritizer circuit and an AND gate for combining the outputs of the set of OR gates, are employed to generate a set of acknowledge signals for the smart devices.

Abstract: A low profile electronics cabinet for a computer workstation or personal computer formed of structural foam includes a plurality of ribs forming a support grid molded into the bottom, internal surface of the cabinet top and a plurality of vertical supports molded into the top, internal surface of the cabinet base. When assembled, the support grid rests upon the vertical supports, the support grid and vertical supports functioning to transfer the weight of a load placed on top of the cabinet to the cabinet base.

Abstract: A disk array controller providing a variable configuration data path between the host system and the individual disk drives within a disk array and parity and error correcting code generation and checking. The controller includes host interface logic for converting data received from the host system via a 16 or 32-bit SCSI bus to 16, 32 or 64-bit data words multiplexed across one, two or four 16-bit buffer busses, and for converting data received from the buffer busses to the proper form for transmission to the host system. A bus switch, including an exclusive-OR circuit for generating parity information, is connected between the buffer busses and six disk drive busses for directing the transfer of data and parity information between selected buffer and drive busses. The controller further includes a storage buffer connected to the buffer busses to provide temporary storage of data and parity information.

Abstract: A stepping motor has an attached encoder which provides automatic commutation point alignment for maximum efficiency and torque during closed-loop operation. Novel use of a fine line encoder along with a phase mapping circuit permit shaft/rotor alignment of the stepping motor with minimum commutation errors, and without the need for manual adjustments.

Abstract: An interrupt signal for a disk array is generated by selectively combining interrupt signals received from the individual disk drives and other interrupt signal sources within the disk array. The circuit for generating the array interrupt signal includes logic for combining a first group of selected interrupt signals to generate a group interrupt signal having a HIGH state when each one of the signals in the first group is at a HIGH state, and logic which combines a second group of selected interrupt signals to generate an independent interrupt signal having a HIGH state when any one of the interrupt signals of the second group is at a HIGH state. The group and independent interrupt signals are gated together through use of an OR gate to generate the disk array interrupt signal. The logic for generating the group and independent interrupt signals can be reconfigured to combine, pass or ignore interrupt signals as selected by the system user.

Abstract: Apparatus for correcting the byte alignment of multiple-byte data words during DMA word transfers. The apparatus includes a four-byte input word bus and a four-byte output word bus. A carrier register stores the second, third and fourth bytes of a first four-byte data word received on the input bus. A data selector including four 4:1 multiplexers determines which of the three stored word bytes and which of four bytes corresponding to a second data word received on the input bus should be placed on the four-byte output word bus and the sequential order of the bytes on the bus.

Abstract: An interface device between, and a method for providing data from, one of a plurality of optical or magnetic media reader devices to a host is disclosed. The interface device comprises first and second input ports, each port being connectable to a selected media device. The device also comprises means for automatically identifying the type of media device connected to each of the ports by sequentially sampling control or data signals therefrom. It also includes means for determining when an identified media device is active by sampling control or data signals from each port that has an identified media device connected thereto.

Abstract: A high speed, D-type flip-flop is implemented using eight complementary metal-oxide semiconductor (CMOS) tristate inverters. The flip-flop includes both D and D/ data input terminals and parallel data paths from the data input terminals to Q and Q/ output terminals. The improved circuit design realizes higher operating speed than prior CMOS flip-flops by eliminating the inverter delays present in single path flip-flops and providing only two gates in the data paths between the input and output terminals.

Abstract: A video controller which can be programmed to generate horizontal and vertical blanking and synchronization signals for driving video monitors having different resolutions or operating frequencies includes storage registers for receiving and storing pixel count information associated with the beginning of horizontal blanking, the beginning of horizontal synchronization, the end of horizontal blanking, the end of horizontal synchronization and line count information associated with the beginning of vertical blanking, the beginning of vertical synchronization, and the end of vertical synchronization. The controller further includes circuitry for counting pixels as they are provided by the controller to the monitor and circuitry for counting horizontal scan lines. Properly timed blanking and synchronization signals are generated by comparing pixel count and line count information to the stored pixel and line count values.

Abstract: A modular cabinet for enclosing a plurality of disk drive canisters. The cabinet includes left and right sides and a center section, each formed of molded structural foam. Each side includes horizontal top and bottom portions which include tongue-like projections for mating with similar features in top and bottom portions of the center section. The sides and center section are secured together through the use of four latching members which cooperate with features molded into the sides. The design of the components permits easy assembly of the cabinet without the use of tools. Horizontal rails molded into the internal surfaces of the sides and both surfaces of the center section form the bays for receiving disk drive canisters.

Abstract: An improved sample-and-hold circuit includes a first MOSFET transmission gate connected between an analog input voltage and a storage capacitor. The first transmission gate is constructed to have low on resistance and operates for a predetermined period of time to rapidly charge the capacitor to input voltage. A second, smaller MOSFET transmission gate having reduced charge injection characteristics is connected in parallel with the first gate. The second gate is turned on coincidentally with the first gate but remains on for a short period of time after the first gate has been switched off.