Abstract: A card reader (16) having a single entry slot (18) for cards (2), and an electronic control means (35) for controlling the operation of the reader (16). The reader (16) further includes a smart card reading section (26) incorporating a plurality of terminals (34,38,36) respectively adapted to read contact smart cards, inductive contactless smart cards and capacitive contactless smart cards. A pair of endless belts (28) are arranged to form a feed path (30) there between. A card (2) inserted through the entry slot (18) is received between the endless belts (18) and transported through the card reader (16) and positioned in the smart card reading section (26) so that smart card terminals (6,8 or 10) on the card (2) are located beneath corresponding smart card terminals (34,36 or 38) in the card reader (16). Data can then be read from the card (2) if the card (2) is a contact smart card, an inductive contactless smart card or a capacitive contactless smart card.

Abstract: An apparatus for assessing the condition of a bank note includes a vacuum pump (4), an air flow detector (8) for producing an electrical output indicative of air flow through the detector (8), and a suction device (10) connected to the vacuum pump (4) via the air flow detector (8). In operation, a bank note is fed from an entry slot into cooperative relationship with the suction device (10) such that the bank note covers, and is sucked against, the suction device (10). An electronic control device is coupled to the detector (8) and is arranged to make a determination of the condition of the bank note based on the electrical output of the detector (8), this output being representative of the porosity of that part of the bank note sucked against the suction device (10).

Abstract: In a high speed digital computer data transfer system, a data bus driver, implemented using complementary metal-oxide-semiconductor (CMOS), reduces data bus voltage swings between logic high and logic low levels by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. Voltage overshoot and undershoot of the reduced bus logic levels are prevented by two "clamping diode" transistors. One of the two clamping diodes connected to the data bus is biased to a point just below conductivity, while the second clamping diode is biased to a point just below conductivity. As a result, if the output voltage rises above a selected level, the first clamping transistor acts as a conducting diode to pull the output voltage down, and, in a similar manner, if the output voltage at node falls below a selected level, then the second clamping transistor functions as a conducting diode to pull the output voltage up to an acceptable level.

Abstract: An electric circuit board including EMI shielding. The board comprises a substrate including top and bottom surfaces and at least one internal ground layer, the internal ground layer being electrically insulated from the external surfaces of the substrate. A plurality of vias are formed in the substrate near the edges of the substrate, each via providing an opening from the surface of the substrate to the internal ground layer A metal plating is applied to the vias, the edges of the substrate and the perimeter of the surface of the substrate, the metal plating along the substrate perimeter being applied over the plated-up vias to electrically connect the ground plane with the metal plating applied to the edges of the substrate.

Abstract: An improved CMOS driver circuit for driving a fast, single-ended, wired-or bus architecture. The driver circuit provides a user-selectable active deassertion assist feature which assists a passive terminator circuit in quickly pulling-up a data or control bus line. The resulting driver circuit provides greater noise immunity to negative voltage transients that result from impedance mismatches caused by poor cable design configurations.

Abstract: Resistive ink elements are applied to the exposed surfaces of thin sections or thermal insulation provided to cooled integrated circuit devices within a computer system. The insulation is made thinner than required to prevent the formation of condensation upon the exposed surfaces of the insulation in order to accommodate space limitations within the computer system. The resistive ink elements generate heat upon the application of an electrical current thereto to warm the exposed surfaces of the insulation to a temperature above the dew point of the ambient environment within the computer system, thereby preventing the formation of condensation on the surfaces on the insulation.

Abstract: An architecture for on-line reconfiguration on a RAID level 0, 1, 2, 3, 4 or 5 disk array. This architecture allows the computer system to perform reconfiguration of the disk array transparently, with disk I/O operations being performed concurrently with reconfiguration operations. The reconfiguration process allocates computer system resources necessary to support both the old and new array configurations during the reconfiguration process. Logical areas within the array are sequentially reconfigured from the old configuration to the new configuration. Data in each logical area is read from the area undergoing reconfiguration and thereafter overwritten in accordance with the new array configuration. System I/O requests received during reconfiguration which are directed to unreconfigured areas in the disk array are executed in accordance with the old array configuration.

Abstract: A method for partitioning a disk array into logical storage units distinct from the physical storage units within the array. A set of individual drives within the array are partitioned into multiple partitions. Corresponding partitions from the individual drives are grouped together to form a logical unit which is addressed as, and functions as, an independent disk array. The partitions within the logical unit are addressed as, and function as, disk drives within the logical array. Thus, a single set of disk drives may be divided into two or more logical storage units, each functioning as an independent disk array, and each employing a different RAID level scheme for storing data. Alternatively, multiple sets of disk drives within the array can combined together into a logical storage unit which functions as a single set of drives. Corresponding drives from each set of drives are addressed as a single disk drive within the logical unit.

Abstract: A wireless local area network (10) including a plurality of stations (12) utilizes dynamic transmit power level control such that only the power level needed for reliable transmission to a particular station (12) is utilized. Each transmitted information packet (80) contains a byte (92) representing the power level at which the packet (80) was transmitted. The power level at which the packet (80) is received is measured and a path attenuation value is calculated, averaged over a plurality of packets and utilized, together with a measured interference level also transmitted in the packet (80), to determined a transmit power level for that path. Also determined is an associated defer threshold level. The transmit power levels and associated defer threshold levels are stored in a table (270).

Abstract: A data storage system comprising a matrix of intelligent storage nodes interconnected to communicate with each other via a network of busses. The network of busses includes a plurality of first busses for conducting data from and to a corresponding plurality of host system processors and a plurality of second busses, each one of the second busses intersecting with each one of the first busses. The nodes are located at each intersection. The storage nodes each include a data storage device, such as a magnetic disk drive unit, a processor and buffer memory, whereby the node processor controls the storage and retrieval of data at the node as well as being capable of coordinating the storage and retrieval of data at other nodes within the network.

Abstract: A programmable read only memory (PROM) including an array of polysilicon fuse elements. The fuse array is formed within a semiconductor substrate including first and second patterned signal layers electrically insulated from one another. Each polysilicon fuse element within the array connects a first electrical conductor residing in the first patterned signal layer with a second electrical conductor residing in the second patterned signal layer. The polysilicon fuse element is in the form of a narrow strip and is folded in order to cause a current flowing through the clement to crowd, lowering the amount of current required to heat the fuse element to its melting point, i.e. the threshold current. The PROM is programmed by passing a threshold current through selected fuse elements.

Abstract: A method for assuring consistency between data and parity in a disk array system following a reset or a power failure condition which interrupts the execution of write I/O operations. The method includes the steps of: examining drive activities to identify unfinished write I/O operations due to an interrupt condition; logging information necessary to identify the unfinished operations and the array redundancy groups associated with the unfinished operations into a non-volatile memory; and checking for log entries in the non-volatile memory during a disk array subsystem initialization or the restoration of power. For each unfinished operation identified in the log, the method further includes the steps of: performing a bit-wise exclusive-OR of corresponding portions of the data stored within the associated redundancy group to calculate parity consistent therewith; and writing the calculated parity to the parity storage areas within the associated redundancy group.

Abstract: A memory packaging scheme for high speed computer systems includes, several memory module sockets mounted to a printed circuit board and interconnected by a common set of address, data and control transmission lines within the printed circuit board. The transmission lines are interrupted at each connector. Cooperating memory modules, such as SIMM memory modules are installed in sequence into one or more of the module sockets in accordance with the requirements of the computer system. Installation of a memory module into a memory socket closes the open circuits for each one of the transmission lines at the memory socket, extending the uninterrupted length of the transmission lines to the next memory socket in the sequence.

Abstract: In apparatus for detecting counterfeit bank-notes, an electronic camera forms a digital representation of a small area of the bank-note. The digital image is stored in an image memory. The Fourier transform of the digital image is then computed and analyzed to determine if it contains high spatial frequency components, and if so, the note is identified as counterfeit. The analyzer may use pattern recognition techniques. In a modification, Fourier transforms of a plurality of small areas are formed and averaged and the average is analyzed. This invention is particularly suitable for identifying counterfeit bank-notes having regular patterns e.g. of lines or dots, therein, such as are produced by color photocopiers or offset lithography printing.

Abstract: Within a document printing system, a dot generator for determining dot ON/OFF states for a multiple channel matrix print head includes a RAM memory in which is stored print characters received from the print system. The received print characters are stored in ASCII format in predetermined character box memory locations within the RAM memory. The dot generator further includes a ROM memory having (1) a first storage area containing an association table correlating each one of the dot print addresses or locations within the document print zone with one of the character box memory locations within the RAM memory; (2) a second storage area containing an association table correlating each one of the dot print locations with a character box print location row and column number; and (3) a third storage area containing dot state ON/OFF values corresponding to each row of each standard ASCII character. A ROM lookup procedure is utilized to determine the ON/OFF state for each dot location within the print zone.

Abstract: A voltage controlled current source including feedback circuitry which eliminates the need for a current sensing resistor in series with the output voltage controlled current source. The feedback circuit includes circuitry for generating a reference current which is proportional to, but much smaller than, the output current produced by the current source, and current mirror circuitry for generating a sense current which is equivalent to the reference current. The sense current is provided to a current sense resistor, across which a feedback voltage is developed. The voltage controlled current source further includes an amplifier connected to receive an input control voltage and the feedback voltage for generating the output current in response to the input control voltage and the feedback voltage.

Abstract: A star coupler device for interconnecting processors within a data processing system. The star coupler device includes first and second level star couplers. The first level star coupler includes a plurality of inputs and corresponding outputs and functions to logically OR together all signals received at its inputs to generate a first output signal. The second level star coupler also includes a plurality of inputs and corresponding outputs, one of the inputs to the second level star coupler being connected to receive the first output signal. The second level star coupler functions to logically OR together all signals received at its inputs, including the first output signal, to generate a second output signal which is provided at each of its outputs. A switch or multiplexer directs either the first or second output signal to each one of the outputs of the first level star coupler.

Abstract: A multi-chip module wherein electrical components, such as integrated circuit devices, are packaged in a three dimensional arrangement. The multi-chip module includes a first, or upper, substrate including a signal layer formed on the top surface of the substrate and at least one integrated circuit device mounted to the top surface of the substrate and electrically connected to the signal layer. The module further includes a second, or internal, substrate, also including a first signal layer formed on the top surface of the substrate and at least one integrated circuit device mounted to the top surface of the substrate and electrically connected with the signal layer formed on the top surface of the second substrate. The second substrate includes a cavity through the substrate corresponding to each integrated circuit device mounted thereto.

Abstract: A disk drive within a disk array is utilized to capture the original image of data blocks that are updated, i.e., written over, through normal array processes during backup operations. The method captures original data images in a manner that allows the array to be restored to the state that existed at the initiation of the backup process. During execution of backup procedures data is moved in logical block sequence (0 to N) from the array to a backup device, such as a magnetic tape backup device, continuing until all array data has been transferred. Should a write request be received by the disk array controller during backup, the block address associated with the write request is checked to determine if the original data at that address has been written to the backup device. If the original data residing at the target block address has been written to the backup device the write request is scheduled for execution by the array controller.

Abstract: An electronic socket pin for use with sub-cooled integrated circuit devices. The socket pin design provides lower thermal conductance and electrical signal path resistance than a traditional electronic socket pin. The improved socket pin has a tubular body formed of an electrically conductive material having a low thermal conductance, such as 304 stainless steel. The tubular body is open at one end, and has a first diameter at the open end, for receiving an integrated circuit device signal lead. The remainder of the length of the tubular body has a second diameter which is much narrower than the first diameter. This narrower cross section further reduces the thermal conductance of the electronic socket pin. A contact sleeve having a cylindrical body including radially inwardly extending, resilient, prongs formed into the wall of the sleeve is fitted over the open end of the electronic socket pin.