Abstract: An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a first channel region (112) disposed on the first gate region and a source (110) and drain (114) formed on either side of the first channel region. The FinFET transistor (N3) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure (102), having a second channel region (118), and a source (116) and drain (120) formed on either side of the second channel region, and a second gate region (122) comprised of the semiconductor layer, disposed on the second channel region.

Abstract: A method is provided to speed up timing optimization after placement by parallelizing the optimization step. The method includes performing multiple partitions in the set of timing critical paths such that each partition can be optimized independently in a separate processor. To eliminate the need for inter-processor communication, conditions of timing independence and physical independence are imposed on each partition, thereby defining sub-sets of endpoints and paths associated therewith. The optimizing is performed in parallel by the processors, each of the processors optimizing timing of the paths associated with the endpoints in respective sub-sets. In a preferred embodiment, an endpoint graph is constructed from the list of critical paths, where the endpoint graph has at least one vertex representing critical paths associated with a given endpoint. The partitioning step then includes the step of partitioning the endpoint graph to define sub-sets of vertices.

Abstract: A method is described for dynamic stitching of a new module of executable code in a parallel processing environment, where access to a data object is shared by the new module and another module previously loaded. A new data object is created for shared access by the new module and by the other module; a data freshness indicator is updated in accordance therewith. A pointer value for the data pointer associated with the other module is modified, thereby terminating reference to an old data object previously accessed and substituting reference to the new data object. A second data freshness indicator is updated in accordance with access by the other module to the new data object. The old data object is deleted when a comparison between freshness indicators shows that access to the old data object is no longer required.

Abstract: The invention permits an effective traffic flow control, down to all sub-ports, of a switch made of a N-port core switch fabric. Sub-ports concentrate traffic from lower speed lines to a switch fabric native port. In each sub-port adapter, when congestion is detected in the OUT leg, it is reported through the corresponding IN leg. Congestion is piggybacked over the incoming traffic entering the input port of the N-port core switching fabric and is broadcast so that all sub-ports become aware of the detected congestion in any of the sub-ports. Each sub-port adapter performs a checking of the congestion status of all the other sub-ports and acts to stop forwarding received traffic destined for congested sub-ports and holds further received traffic until the sub-ports are reported to be no longer congested. The full intrinsic performance of a N-port switch fabric is realized by concentrating, through port and sub-port adapters, the traffic of more than N independent lines.

Abstract: A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

Abstract: A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface.

Abstract: A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.

Abstract: A bubble level suitable for spaces that are restricted in the vertical dimension has a 45 degree prism attached to the top surface, so that the image of the bubble vial is deflected along a horizontal axis. The prism is optionally rotatable to permit changing the viewing angle in a horizontal plane.

Abstract: A multi-layer module for packaging an electronic component comprises an uppermost electrically conductive layer for mounting the component, a plurality of electrically insulative layers, and a plurality of electrically conductive layers disposed between the insulative layers. The electrically conductive layers form staggered placements of at least three voltage and/or ground distribution layers close to the module surface without signal wiring layers in between, and signal distribution layers comprising signal conductors. Vias form conductive paths through the insulative layers and conductive layers; the corresponding signal, voltage and ground distribution layers are electrically connected with each other and with the uppermost layer.

Abstract: A method is described for facilitating implementation of an automated system for transacting business, where the system users are subject to predetermined rules governing business conduct. Each user is assigned a user ID and has a security profile, which lists the transactions that user is authorized to perform. A list is prepared of pairs of incompatible transactions (transactions which, if performed by the same user, would violate the predetermined rules). Each security profile is compared with the list, to identify security profiles including at least one pair of incompatible transactions. A report is then generated indicating those security profiles which include incompatible transactions and the user identifiers associated with those security profiles.

Abstract: A liquid crystal power supply is provided which generates a high-precision drive power supply voltage supplied to a driver circuit by using a low-precision reference voltage generating circuit. The power supply circuit includes a DC/DC converter which generates a voltage having a size based on an oscillation signal from a power supply voltage and outputs the generated voltage as a drive power supply voltage; a stabilized power supply circuit which generates a highest-level reference potential for generating a gray-scale voltage in a driver circuit; a comparison unit which outputs a difference voltage according to a difference between the drive power supply voltage and the highest-level reference potential; an internal reference voltage generating unit; an error amplifying unit which amplifies a difference between the reference voltage and the difference voltage; and a PWM conversion unit which outputs an oscillation signal in response to the amplified difference.

Abstract: A method and apparatus are provided for fault location in a loop network (100, 200, 400). The network system having a host port (214) for supplying and receiving data and a plurality of successively connected ports (201, 202, 203, 204, 205) through which data from the host port (214) is transferred. A counter (122) for each port records data transfers in which the amount of data received at a destination port is less than an expected amount of data. When a transfer with less than the expected amount of data is identified for a data flow between a sending port (201) and a destination port (214), the counters are incremented for each port (202, 203, 204, 205, 214) after the sending port up to and including the destination port. Analysing means determines a fault location in the network system from the distribution of counts in the counters (122).

Abstract: A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin?) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.

Abstract: A clamping flexure for use in a vacuum employs a spring-loaded shaft that pulls an object being supported against a support piece, including a mechanism, passing through the vacuum vessel, for releasing the spring tension during adjustment, the shaft being sufficiently compliant that restoring force after adjustment is less than a threshold value so that displacement of the shaft does not impress a force on the object being supported that returns it toward its position before adjustment.

Abstract: An e-beam system generates a set of massively parallel beams of order of magnitude 1,000 by employing a flash eprom to store calibration data and to receive on/off signals directed through the address system of the memory array, the individual electron sources being mounted above the memory array in a geometric array that tracks the structure of the memory array.

Abstract: A system for burn-in testing of integrated circuits employs a cooling module with an aperture that accommodates a standard size holder for various chips, the holder being placed in the mouth of the aperture, in contact with a flexible seal. When the module is raised to make contact from below with a socket on a test board, the seal confines the cooling fluid and contacts on the upper surface of the holder are pressed against a set of corresponding contacts on the test board.

Abstract: The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETS, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

Abstract: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads.

Abstract: The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.