Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.

Abstract: A method is described for forming a metal pattern in a low-dielectric constant substrate. A hardmask is prepared which includes a low-k lower hardmask layer and a top hardmask layer. The top hardmask layer is a sacrificial layer with a thickness of about 200 Å, preferably formed of a refractory nitride, and which serves as a stopping layer in a subsequent CMP metal removal process. The patterning is performed using resist layers. Oxidation damage to the lower hardmask layer is avoided by forming a protective layer in the hardmask, or by using a non-oxidizing resist strip process.

Abstract: A diffusion barrier that has a low dielectric constant, k, yet resistant to oxygen and/or moisture permeability is provided. The diffusion barrier includes a dielectric stack having at least two or more dielectric films, each film having a dielectric constant of about 8 or less, wherein the dielectric stack comprises alternating films composed of a high-permeability material and a low-permeability material. A semiconductor structure including substrate having at least one wiring region and the inventive diffusion barrier formed on a surface of the substrate is also provided.

Abstract: A method for making a metal-insulator-metal capacitive structure includes depositing a copper barrier and seed layer over a support structure such as an inter-level dielectric layer, forming a dielectric over the copper barrier and seed layer, and then forming a forming a metal layer over the dielectric. The copper barrier and seed layer forms a bottom plate of a capacitor, and the metal layer forms the upper plate which is separated from the bottom plate by the dielectric. By forming the bottom plate from a copper barrier and seed layer, reduced sheet resistance and surface roughness is achieved, both of which enhance the performance of the capacitor. This performance is further enhanced by forming the capacitor to have a damascene structure. Preferably, at least one conductive interconnect is formed simultaneously with the formation of the capacitor. This is made possible, at least in part, by forming the interconnect using a plate-through mask technique.

Abstract: The present invention provides a permanent protective hardmask which protects the dielectric properties of a main dielectric layer having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask further includes a single layer or dual layer sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers and the permanent hardmask layer may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants.

Abstract: Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET devices, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET devices can be enhanced. A method for making the devices is included.

Abstract: A multi-beam e-beam system employs a set of independently controllable (for blanking and deflection) subsystems placed in a solenoid field, each system having a demagnifying lens comprising at least one passive pole piece, so that the final image demagnifies imperfections in the upstream electron beam. Upper and lower sections of the system employ the focusing effect of the solenoid field to form an image at a shaping aperture and a demagnified image of the beam at the shaping aperture on the workpiece. Small focus corrections due to magnetic lens field non-uniformity and/or target height variations, are accomplished with an electrostatic unipotental lens built into the pole pieces and target voltage variations.

Abstract: In a gate array having adjacent lines of PFETs and NFETs along a first axis, some gates of PFETs and/or NFETs extend into the region between wells and along a first (x) axis of the lines of transistors to overlap along the axis, so that an extended gate of an nth transistor, a gate of an (n−1)th non-extended transistor and a gate of an (n−1)th non-extended transistor of the opposite polarity lie along an axis (y) perpendicular to the first axis. In a rectangular layout, the upper right transistor (having an extended gate) is connected to the lower left transistor by a short connection along the y axis.

Abstract: Steep concentration gradients are achieved in semiconductor device of small sizes formed on SOI or double SOI wafers by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects. In the case of SOI wafers greater uniformity of electrical characteristics are achieved using the high quality of semiconductor material made available therein consistent with the relatively thin active layer.

Abstract: Credit card or portable identification cards containing smart card technology and electronic fuse (e-fuse) technology are combined with an LFSR pseudo random number generator to provide a secured method to prevent fraud and unauthorized use. Secure personalization via e-fuses, a pseudo-random number generator linear feedback shift register, free running clock oscillator, and power source embedded in the card provide a highly secured method to render a lost or stolen card useless. A unique card ID is permanently encoded within the card which requires a specific activation code to activate the card. A PIN number permits the card owner to activate the card for a predetermined length of time while processing a transaction. The card dynamically generates random code sequences and synchronization keys to secure a transaction.

Abstract: A process is described for integrating an optoelectronic chip and a driver chip on a substrate, in which a waveguide is built into the substrate and the chips are joined to the substrate using a stud/via alignment technique. The waveguide structure includes a reflector and a channel for transmitting light emitted by the optoelectronic chip. A stud formed on the substrate is aligned to a via formed in a layer on the chip, aligning the chip so that the light reaches the reflector and enters the waveguide. A driver chip may be mounted on the substrate in close proximity to the optoelectronic chip.

Abstract: An electron beam system employs a non-saturating detector for measuring total beam current that comprises a thin membrane of only a few microns thickness placed before a detector and separated from the detector by a drift space of about 10 mm, so that electrons in the beam are not absorbed to any significant extent, but are scattered transversely to spread the beam and avoid local saturation of the detector.

Abstract: In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trench and undercutting the insulating layer laterally permits the buried strap from the capacitor center electrode to make contact to the back side of the SOI layer, thereby increasing the vertical separation between the passing wordline and the strap.

Abstract: A multi-beam shaped-beam electron beam lithography system employs conventional lenses and magnetic deflectors, with an array of lithographically fabricated electrodes disposed about a central axis to simultaneously and independently deflect electron beams in beamlet exposure ranges separated transversely from one another within a subfield, so that subfields overlap.

Abstract: A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.

Abstract: A method and structure for searching a computerized network of databases containing documents uses a web crawler. The web crawler is provided with conceptual guidelines before the searching. The invention summarizes and performs text clustering on the summaries to produce classifications. The text clustering is performed using seeds based on the conceptual guidelines. The invention then provides, through a user interface, the classifications and a query entry to search the classifications and directs (in response to the query entry) the user to one or more of the classifications, such that the user is directed to the classifications (and hyperlinks to the documents) and the user is not provided the documents themselves.

Abstract: A method for forming an isolation trench in a silicon or silicon-on-insulator substrate is described in which a trench is formed in the semiconductor structure (containing a multiple layer structure of Si, SiO2, and SiN layers) and an undoped polysilicon layer is deposited on the bottom and sidewalls of the trench and on the surface of the region adjacent to the trench. A substantial portion of the trench is left unfilled by the undoped polysilicon layer deposited. The polysilicon layer is thermally oxidized to form a thermal oxide that fills the trench and thereby avoids forming a birds-beak formation of the thermal oxide above the sidewalls of the trench. The isolation structure may be planarized by either removing the polysilicon layer from the region adjacent to the trench before oxidation or later removing the oxide from the SiN layer and adjusting height of the oxide in the trench.

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Abstract: A technique is described, based on concepts of halftone printing, for controlling feature dimensions in a printed image at increments smaller than the smallest addressable unit of the template used to produce that image. Accordingly, photomasks may be fabricated to yield images with sizes differing from a nominal width by increments which are small fractions of the minimum template size or pixel size. A template fabricated according to this technique includes a feature having one or more edges, and a first array and a second array of shapes (protrusions or indentations) disposed on the edges. The first and second arrays have respective segmentation periods; the first and second segmentation periods are different. Each array is formed of a plurality of identical shapes repeating at every corresponding segmentation period, each shape having a predetermined length and a predetermined width.

Abstract: Forming poles from sectors of a tube of carbon or a material with similar conductive properties and supporting the poles by bonding an insulating support ring thereto before removing end rings formed at the ends of the tube which temporarily support the poles provides a multipole deflector element of robust structure of high dimensional accuracy and stability in which eddy current and charging effects are avoided. The manufacturing method is much simplified, reduced in cost and increased in reliability, repeatability and yield over manufacturing techniques for known multipole deflectors.