Abstract: A chemical-mechanical polishing (CMP) system and method includes pumping polishing slurry from a CMP apparatus through a sampling tube to an endpoint detection apparatus during a polishing operation, and flushing the sampling tube while a polishing operation is not in progress. The flushing of the sampling tube is commenced in accordance with a control signal from the endpoint detection apparatus terminating the polishing operation; the flushing is terminated in accordance with a starting signal to the CMP apparatus. The pump, which pumps a sample of slurry into the endpoint detection apparatus, continuously pumps slurry and/or water. Clogging of the slurry sampling tube is thus eliminated, thereby ensuring robust operation of the CMP apparatus. Contamination of the sampling tube is also avoided, so that the system may reliably provide sensitive endpoint detection and process control, even when a film of low pattern density is polished.

Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The MEMS has an anchor portion having a conductor therethrough, by which it is connected to a substrate. The chip is attached to the MEMS substrate in a direction normal to the substrate surface, so as to make a conductive path from the chip to the MEMS. The chip may be attached by bonding the conductor to C4 metal pads formed on the chip, or by bonding the conductor to metal studs on the chip. The MEMS substrate may be thinned before attachment to the chip, or may be removed from the underside of the MEMS. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.

Abstract: A computer memory structure for parallel computing has a first level of hierarchy comprising a plane. The plane contains a thread which represents an independent flow of control managed by a program structure, a heap portion for data structure, a stack portion for function arguments, and local variables and global data accessible by any part of the program structure. The memory structure further has a second level of hierarchy comprising a space. The space contains two or more of the planes, with the planes in the space containing the program structure. The space further contains common data accessible by the program structure between each of the planes. A third level of hierarchy in the memory structure comprises two or more of the spaces. The spaces contain the same or different program structures, and common data accessible by the program structure between each of the spaces.

Abstract: A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

Abstract: Fine positioning of a shaped or patterned charged particle beam without use of intrusive fiducial marks is achieved by providing a dithered shadow pattern, preferably in the form of a grid, within the shaped or patterned charged particle beam. Light output from fiducial marks preferably formed of a scintillating material is reduced when the dithered shadow pattern is incident on some or all of the fiducial marks. The timing of the incidence of the shadow pattern on fiducial marks indicates the position of the shaped or patterned charged particle beam such that correction of the beam position on the target can be corrected to a small fraction of system resolution. The dither pattern and repetition period is chosen to avoid interference with uniformity of beam illumination of the target. Feedback of position error thus provides phase locked position correction in real time and is suitable for mask making since the fiducial marks are not intrusive.

Abstract: A system for supporting and adjusting the position of an object in a vacuum includes inner and outer support rings that are connected by flexible mounts that are compliant along one axis and stiff along other axes, and drivers extending through the wall of the vacuum chamber that move the supports independently along their respective axes. At least the inner support is clamped after adjustment by a clamp that exerts a strong clamping pressure while exerting transverse force only less than a threshold selected to avoid motion after adjustment.

Abstract: In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trench and undercutting the insulating layer laterally permits the buried strap from the capacitor center electrode to make contact to the back side of the SOI layer, thereby increasing the vertical separation between the passing wordline and the strap.

Abstract: A converter circuit for converting a double width data bus (transmitting data at a single rate) to a single width data bus (transmitting data at a double rate). The circuit operates with a single clock, using the clock (positive clock) and its complement phase (negative clock) to process a set of even data and odd data. The circuit has a data mixer stage and an XOR stage. Even and odd data are mixed, using multiplexors and the positive and negative clocks, to generate mixed data. An XOR function is performed on the mixed data, using NAND gates. Using NAND gates to perform the XOR instead of a multiplexor ensures synchronous output timing, and ensures that the two stages are fully testable according to any scan-chain test method.

Abstract: A method and apparatus for clamping a semiconductor mask to a carrier device is taught. The apparatus is comprised of a base member to which is attached an elongated spring. Both the base and the spring have affixed to them a means for compressively contacting the mask surface when the mask is put in place. In the preferred embodiment, that contact means is made of sapphire shaped in the form of a dome. The clamp further includes an adjustment screw that can be used to adjust the height of the contact means affixed to the base member. In this manner, the surface of the mask can be adjusted so that it is planarized to the right orientation relative to an e-Beam or laser source that will be used to scribe a pattern on the mask. Finally, the clamp includes electrical contacts, and the materials out of which the clamp is made are deliberately selected, so that no electrical or magnetic forces can build up on the clamp or the wafer that might adversely affect the scribing process.

Abstract: The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

Abstract: An apparatus and method for reducing noise and resonance detractors connected with and E beam tool. The invention provides a plurality of embodiments. In one embodiment, the E beam tool will be calibrated and the results will be then filtered to counter the effects of the noise afterwards. In an alternate embodiment of the present invention, a filter is applied in the actual feedback of the E beam tool for the writing cycle.

Abstract: An apparatus and method for detection of electromechanical and mechanical errors in an electron beam device is provided. First the existing subfield is divided into a gridlike structure where each grid can be considered a target. Then a plurality of target points are provided on each grid for measuring combined directional variances. The separated horizontal and vertical variances is also measured for each of the target points. This leads to the performance of a significance tests, based on the F statistic which we refer to as FHV, for horizontal and vertical values of each target points during which FSTITCH values are also obtained. The FSTITCH values are then compared for horizontal and vertical values and an error alert provided when there is a sufficiently large disparity between the separated FSTITCH values. In an alternate embodiment of the present invention, a three dimensional grid is also provided to be used in a similar manner.

Abstract: As disclosed herein, a system and method are provided for detection and measurement of noise on E beam tools and devices including a spectrum analyzer which looks at the different frequency components of the noise. The deflected electron beam from the tool is calibrated in a coarse and fine mode by scanning the beam over a grid-like calibration target. The position of where the bars are detected is compared to where they actually are, and the deflection can be calibrated so that it matches the grid. This invention can utilize a Fast Fourier Transform (FFT) of the time-ordered data which allows one to see peaks associated with noise.

Abstract: An apparatus for plating and planarizing metal on a substrate includes a plurality of dispensing segments, each having at least one hole for dispensing electroplating solution onto the substrate. The dispensing segments form a circular counterelectrode and are movable with respect to each other during an electroplating process, so that the counterelectrode has a variable diameter. The electroplating solution is thus dispensed on an annular portion of the substrate having a diameter corresponding to the diameter of the counterelectrode; accordingly, the variable-diameter counterelectrode permits localized delivery of the plating solution to the substrate.

Abstract: A method and apparatus are described for performing both electroplating of a metal layer and planarization of the layer on a substrate. Electroplating and electroetching of metal (such as copper) are performed in a repeated sequence, followed by chemical-mechanical polishing. An electroplating solution, electroetching solution, and a non-abrasive slurry are dispensed on a polishing pad in the respective process steps. The substrate is held against the pad with a variable force in accordance with the process, so that the spacing between substrate and pad may be less during electroplating than during electroetching.

Abstract: A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

Abstract: A method and structure for a memory structure that includes a plurality of substrates stacked one on another is disclosed. The invention includes a plurality of connectors connecting the substrates to one another and a plurality of memory chip packages mounted on the substrates. The connectors have a size sufficient to form a gap between the substrates. The gap is larger than a height of the memory chip packages.

Abstract: A method of forming an optical disc, and an optical disc formed, so as to facilitate identifying unauthorized copies of the disc by using a defined procedure for reading the disc. The method comprises the steps of encoding digital data, comprised of a series of 0s and 1s, in the disc by forming a series of spaced pits along a track, so that the track comprises a series of pits and lands, and wherein, when said defined procedure is used to read the disc, each of said pits and lands is read as either a 0 or a 1. The method comprises the further step of forming at least one fuzzy area on the track so that when the defined procedure is used to read the disc, the fuzzy area is sometimes read as 0 and sometimes read as 1. With a preferred procedure, the pits reflect a given light beam at a first intensity, the lands reflect the given light at a second intensity, and the fuzzy area reflects the given light at a third intensity substantially midway between the first and second intensities.

Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=K×n). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a “thermometric” coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up.

Abstract: A method is described for noise reduction in a CMP endpoint detection system employing torque measurement. The torque signals are acquired using an adjustable sampling rate and sample size, and averaged using a moving array of adjustable size. By introducing these three adjustable quantities in the torque-based endpoint control algorithm and properly setting their values in the endpoint detection recipe, periodic noise associated with carrier rotation and carrier oscillation can be effectively removed. This in turn permits reliable, closed-loop control of the CMP process.