Abstract: An ionization gas analyzer system includes an ionization chamber including ionization electrodes contained therein. The ionization chamber contains a test gas or gas mixture. A high voltage generator is coupled to the electrodes and provides variable high voltage pulses to the ionization electrodes. An ionization voltage analyzer is coupled to the ionization chamber and receives ionization voltage information from the plurality of ionization electrodes in response to the variable high voltages pulses. The ionization voltage analyzer produces a gas code identifier in response to the plurality of ionization voltages by defining a code based on which of the ionization voltages exceed an arbitrarily established reference level ionization voltage. A single ionization electrode system can be used to determine a concentration of a particular gas.

Abstract: A complex arithmetic processor and method includes a host interface for distributing data, a left memory and a right memory each coupled to the host interface, and a Z memory coupled to the host interface. The left memory and the right memory store the data and the Z memory stores Z memory data. A right/left switch is coupled to the left memory and to the right memory and makes left memory a data source and a right memory a data destination in a first setting, and makes the right memory the data source and the left memory the data destination in a second setting. An arithmetic engine is coupled to the host interface, to the Z memory, and to the left and right memories. The arithmetic engine uses the data and the Z memory data to perform an operation on the data to produce a result.

Abstract: An impedance transforming three-port power divider/combiner includes first, second, and third lumped elements (e.g. 54, 55, and 56). The first lumped element (54) couples the first port (51) and electrical ground. The second lumped element (55) couples the first and second ports (51 and 52), and the third lumped element (56) couples the first and third ports (51 and 53). A resistor (59) is coupled between the second and third ports (52 and 53). Capacitors (57 and 58) couple the second port (52) and the third port (53) to electrical ground. A signal input to the first port (51) results in identical divided output signals at the second and third ports (52 and 53). Signals input to the second and third ports (52 and 53) result in a combined output signal at the first port (51).

Abstract: A non-linear active device (32), such as a FET, multiplies multiplicand signals to generate a product signal. A combining circuit (24) combines multiplicand signals into a combined signal. An input matching and conditioning network (28) couples the combined signal to an input of the active device (32). This network (28) matches impedances between sources for the multiplicand signals and the active device (32) at the frequencies of the multiplicand signals, and desirably shorts the product signal's frequencies. A feedback resistor (36) couples between the output and input of the active device (32) to lower impedance at the output and to stabilize the active device (32). An output matching and conditioning network (40) couples a mixed signal from the output of the active device to an output circuit (42). This network (40) matches impedances between the output circuit (42) and the active device (32) at the frequencies of the product signal, and desirably shorts the multiplicand signals' frequencies.

Abstract: A special functions arithmetic logic unit (ALU) method and apparatus includes an ALU register, an ALU register value processor coupled to the ALU register for receiving and processing ALU register values to produce output data, and a normalizer. The normalizer receives and processes complex memory values to produce normalized output data independently of the output data from the ALU register value processor. The ALU register value processor includes a parser, combiner, polynomial divider, magnitude estimator, and a Hamming distance determiner. The normalizer includes an exponent determiner and first and second scalers for producing normalized X and Y data of the normalized output data.

Abstract: A digital adjustable phase modulator and method includes a first circuit path and a second circuit path for a signal. A fixed bias voltage is coupled to the first circuit path and to the second circuit path which respectively include first and second active variable reactance components such as varactor diodes. The first circuit path and the second circuit path further include chip capacitors to provide a DC block for first and second MMIC single pole double throw switches, and transmission lines for the signal have a length of one-fourth of a wavelength of the signal to provide an RF short. A control voltage is coupled to the first and second varactor diodes such that the capacitances across the first and second varactor diodes changes, resulting in a phase difference between the signal traversing the first circuit path relative to the signal traversing the second circuit path.

Abstract: A bandwidth synthesized radar level measurement system includes a transceiver for generating a transmitted signal and a sweep signal. An antenna coupled to the transceiver sends the transmitted signal toward a level corresponding to a product surface and receives a reflected signal therefrom. A sweep generator generates a chirp slope signal in response to the reflected signal. An intermediate frequency (IF) processor receives the chirp slope signal and a difference signal mixed from the transmitted and reflected signals. The IF processor produces an amplified IF signal and a sweep control receives the amplified IF signal to adaptively control the sweep generator and to produce an output signal including a distance from the antenna to the level corresponding to the product surface.

Abstract: A microwave monolithic integrated circuit (MMIC) differential Schiffman phase shifter includes an input microstrip for receiving an input signal. First and second parallel microstrips produce a phase shifted signal from the input signal. The first microstrip is coupled at a first end to the input microstrip and at a second end to an end microstrip. The second microstrip is coupled at a first end to the end microstrip. An output microstrip is coupled to the second microstrip at a second end of the second microstrip and the input microstrip and the output microstrip are capacitively coupled. The output microstrip produces an output signal from the phase shifted signal.

Abstract: A biphase modulator without matching elements includes a Lange coupler (5) including first, second, third, and fourth ports (1,2, 3, 4), where the first port (1) receives a RF input signal. FETs (6, 7) each have a source, gate, and drain (19, 17, 18 and 22, 20, 21). The drain (18) of the first FET (6) is coupled to the second port (2), the source (19) of the first FET (6) and the second FET (7) are coupled to electrical ground, and the drain (21) of the second FET (7) is coupled to the fourth port (4). The FETs, are switched at the desired modulation frequency by a control input (16) to the gates (17, 20), alternately providing a zero volt signal and a pinch-off voltage signal which produces a biphase modulated RF input signal at the third port (3) of the Lange coupler (5).

Abstract: A detector/video amplifier (DVA)includes a microwave monolithic integrated circuit (MMIC) detector processor for converting a modulated RF input signal to a baseband signal in video and a MMIC amplifier coupled to and located on a single MMIC chip with the MMIC detector processor. The MMIC amplifier amplifies the baseband signal to the video output signal. The DVA is temperature compensated and achieves detection across the full Ku band (12-18 GHz).

Abstract: A method and apparatus for measuring a level of a material in a tank includes providing a stepped frequency microwave signal to an antenna of a transmitter and receiving in the antenna a received signal from a surface of the material at the level to be measured. A measuring signal containing ranging and calibrating signals is processed in even and odd sample sets input to contiguous narrowband filters formed digitally in a processor using DFT and other algorithms to form true in-phase and quadrature outputs. These outputs are combined and further processed using an interpolation algorithm to isolate ranging and calibration frequency components and to accurately measure the distances represented by such components. The calibration distance associated with the calibration frequency component is compared to a known delay line length and any determined error is used to correct the ranging distance associated with the ranging frequency component.

Abstract: A home health and communications support system and method which includes at least one health support unit for monitoring and supporting a patient, at least one monitoring terminal, and a network server coupled between the at least one health support unit and the at least one monitoring terminal for exchanging information between the at least one health support unit and the at least one monitoring terminal. The health support unit comprises a medication controller, communications module for interacting with the patient, central data processor, and external communications interface. The central data processor stores and manipulates patient data generated by the medication controller and by the communications module for patient interaction. The external communications interface allows access to patient data and accepts external data from an external source.

Abstract: A high isolation microwave module includes a housing floor with mounting surfaces for placing microwave components and housing walls ending in housing wall ends coupled to and projecting from the housing floor. A lid including a lid plate and lid walls ending in lid wall ends projects from the lid plate. The lid walls extend toward the housing floor and the plurality of housing walls extend toward the lid plate but neither the lid wall ends nor the housing wall ends are coupled to the housing floor or lid plate, respectively. A plurality of cavities exist between the adjacent lid walls between the housing and the lid plate and a plurality of irises exist between immediately adjacent housing walls and corresponding lid walls. The irises and cavities act as a multi-section high pass filter to provide attenuation to a microwave signal passing through the module.

Abstract: A method and apparatus for generating two phase-coherent first and second signals with arbitrary frequency ratio includes programming a first numerically controlled oscillator (NCO) with a first frequency word to produce a first NCO output. The first NCO output is processed to produce the first signal. The first frequency word is multiplied in a multiplier to produce a second frequency word which is corrected in phase relative to the first frequency word. A second NCO is programmed with the corrected second frequency word to produce a second NCO output. The second NCO output is processed to produce the second signal.

Abstract: A method for gray level printing using a thermal printhead which includes characterizing the paper to be printed, defining a line of a gray scale image using bitplane data sets, entering the first of the bitplane data sets into a shift register, transferring the first of the bitplane data sets from the shift register to a latch, beginning to print a section of the line of the gray scale image using the first of the bitplane data sets in the latch, entering consecutively the remaining bitplane data sets in the shift register, transferring consecutively the remaining bitplane data sets to the latch, and completing the printing of the section of the line of the gray scale image. Multiple refreshing of data per segment printing enables less than 10 millisecond line (1728 bit) printing in 16 shade gray scale.

Abstract: A quick connection system and method for coupling two housings, e.g. a telephone and special function module, includes a bracket having at least one hole. The bracket comprises a slide latch having a slide latch aperture, with the bracket fastened to the first housing base and extending beyond a side of the first housing so that the slide latch and hole overlap the second housing when the second housing is placed adjacent to the first housing. At least one shear boss is affixed to the second housing. A slide latch receptacle is mounted to the second housing, such that the hole on the bracket receives the shear boss and the slide latch on the bracket receives the slide latch receptacle when the second housing is placed adjacent to the first housing. The slide latch can be engaged to rigidly interlock the first housing to the second housing.

Abstract: A method and apparatus for low power clock generation for high speed applications includes a divider for receiving a high frequency input signal and producing a low frequency input signal controlled to a high resolution. A numerically controlled oscillator (NCO) is coupled to the divider and receives a frequency word and the input signal and produces a phase advance command. The phase advance command is used to produce an output transition command. The output transition command is executed in a phase shifter in response to a phase advance/retard polarity input and a high frequency clock input signal. The phase shifter produces a low-frequency output clock signal.