Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: A testing circuit and method for a phase-locked loop allow measurement of leakage currents in the phase-locked loop components. By forcing the output of the phase-frequency detector to a particular state, the charge pump can be disabled. This disables the effect of feedback in the phase-locked loop, and allowing the output frequency to be determined by the voltage on the control voltage node at the time the feedback is disabled. If there is no leakage, the control voltage, and therefore the output frequency, should remain the same as they were at the moment feedback was disabled. Monitoring the output frequency for changes provides an indication of the presence or absence of leakage. Conducting the test using two different charge pump reference currents allows one to detect leakage resulting from charge pump mismatch.

Abstract: A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of three-leaf aberration in the optical system used to expose a semiconductor wafer through the mask, is altered to break up the three-fold symmetry without altering the semiconductor features that are formed. This accomplished by adding features to the mask that break up the symmetry. One way of achieving that result is to make the added features of “sub-resolution” size that do not produce features on the exposed wafer. Another way of achieving that result is to change existing features that do form structures in such a way (e.g., with optical elements) that changes the relative phase, amplitude or other characteristic of light transmitted through those features.

Abstract: In a computer or microprocessor-based system having a plurality of resources making memory requests of a plurality of banks of memory, a switch-based interconnect system allows multiple simultaneous connections between resources and memory banks, maximizing memory throughput and bandwidth concurrency. The invention is particularly useful in devices having embedded banks of memory, where there are no external constraints requiring use of a bus architecture, but can be used with discrete devices as well.

Abstract: A wetting apparatus (110) for wetting a hydrophilic urinary catheter (103) comprises a wetting receptacle (101) which defines a wetting fluid receiving area (102) for receiving the hydrophilic urinary catheter and a hydrophilic urinary catheter wetting fluid container (106) having a discharge outlet (126) movable from a closed position to an open position on application of a predetermined condition thereto to enable the wetting fluid to be discharged from the wetting fluid container.

Abstract: A membrane applied to the ostium of an atrial appendage for blocking blood from entering the atrial appendage which can form blood clots therein is disclosed. The membrane also prevents blood clots in the atrial appendage from escaping therefrom and entering the blood stream which can result in a blocked blood vessel, leading to strokes and heart attacks. The membranes are percutaneously installed in patients experiencing atrial fibrillations and other heart conditions where thrombosis may form in the atrial appendages. A variety of means for securing the membranes in place are disclosed. The membranes may be held in place over the ostium of the atrial appendage or fill the inside of the atrial appendage. The means for holding the membranes in place over the ostium of the atrial appendages include prongs, stents, anchors with tethers or springs, disks with tethers or springs, umbrellas, spiral springs filling the atrial appendages, and adhesives.

Abstract: A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

Abstract: In a mask-programmable logic device having embedded memory blocks, which device cannot be reconfigured for testing like a full programmable logic device, the embedded memory blocks are tested by forming scan chains from the input-side registers of a plurality of embedded memory blocks, and from the output-side registers of a those embedded memory blocks. Test vectors are clocked into the input-side scan chain and the results are clocked out from the output-side scan chain. The test vectors can be made by concatenating multiple copies of a test vector for one block when the blocks are identical. The method works even where one or more embedded memory blocks are configured as read-only devices, as long as the contents of the read-only devices are known so that one knows what test output to expect.

Abstract: A differential buffer has a bias current that is gated by a signal associated with the buffer, such as its input or output. In a preferred embodiment, the bias current is low when the input is in a steady state, but increases as the input switches, to provide high bias current for faster switching of the output. The input preferably is monitored by a rising edge detector and a falling edge detector to turn on the high bias current as the input switches. The output preferably is also monitored, to turn off the high bias current after the output has finished switching, and a steady state has resumed.

Abstract: Multiple coupled inductors are formed in a well in a semiconductor device. The inductors, which preferably are spiral inductors, are strongly coupled with high quality factors. The coupled inductors may be used as efficient signal splitting and combining circuits.

Abstract: In a computer or microprocessor system having a plurality of resources making memory requests, a caching system includes a source tag generator which, depending on the embodiment, could reside in the requesting system resource, in a bus arbiter, or in a combination of a bus arbiter and a switch arbiter, or elsewhere. The system also includes cache control circuitry capable of using the source tag to make cacheability decisions. The cache control circuitry, and therefore the cacheability decisions, could be fixed—e.g., by a user—or could be alterable based on a suitable algorithm—similar, e.g., to a least-recently-used algorithm—that monitors cache usage and memory requests. The caching system is particularly useful where the cache being controlled is large enough to cache the results of I/O and similar requests and the requesting resources are I/O or similar resources outside the core logic chipset of the computer system.

Abstract: An armature winder having an adjustable winding arm, includes a wire delivery point with two degrees of freedom—one along the longitudinal axis of the armature winder and one transverse to the longitudinal axis of the armature winder. In one preferred embodiment, the adjustable winding arm pivots around an axis transverse to the longitudinal axis of the winder. This pivoting motion allows adjustment of the wire delivery point along an arcuate path, thereby utilizing each of the degrees of freedom simultaneously.

Abstract: A computer system for supporting a plan of counterclaim insurance provided to professionals, optionally along with professional liability insurance, deters frivolous professional malpractice claims. The insurance plan pays expenses, for example, of counterclaims for malicious prosecution when a frivolous claim has been made and tried to a judgment for the accused professional, and an independent review concludes that the claim was frivolous. The names of covered professionals are posted on a publicly accessible database. If potential plaintiffs or their attorneys find a potential defendant's name on the database, they may be deterred from filing weaker claims that might be viewed as frivolous. Upon approval of an applicant for counterclaim insurance, the applicant's name is posted to a public database, which may be accessible through the Internet, including the World Wide Web, or alternatively through a dial-up facility.

Abstract: The preferred orientation, or planar oscillation plane, of a golf club shaft is located by measuring the oscillation of the shaft when a horizontal impulse is applied and from those measurements determining an orientation in which the oscillation would be substantially planar. In a preferred embodiment an iterative process is used to converge on the preferred orientation. The location of the preferred orientation may be marked on the shaft and used to assemble a golf club with the planar oscillation plane in a predetermined orientation. The assembly of the golf club can be done manually—e.g., in a refitting situation—or automatically—e.g., in a new club manufacturing setting.

Abstract: A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.

Abstract: The preferred orientation, or planar oscillation plane, of a golf club shaft is located by measuring the oscillation of the shaft when a horizontal impulse is applied and from those measurements determining an orientation in which the oscillation would be substantially planar. In a preferred embodiment an iterative process is used to converge on the preferred orientation. The location of the preferred orientation may be marked on the shaft and used to assemble a golf club with the planar oscillation plane in a predetermined orientation. The assembly of the golf club can be done manually—e.g., in a refitting situation—or automatically—e.g., in a new club manufacturing setting.