Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

Abstract: Apparatus for displaying still images to viewers in motion relative to those images, such as passengers on a subway train, includes a plurality of images mounted on a surface, and a slitboard mounted between that surface and the viewer. As the viewers pass by, the slitboard acts like a shutter, creating an animation effect. In addition, there is a stretching or widening effect that enlarges the images, allowing images to be “preshrunk,” thereby allowing a large number of images in a small space, increasing the available frame rate of the animation. The stretching effect depends on the distance between the image surface and the slitboard.

Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

Abstract: The preferred orientation, or planar oscillation plane, of a golf club shaft is located by measuring the oscillation of the shaft when a horizontal impulse is applied and from those measurements determining an orientation in which the oscillation would be substantially planar. In a preferred embodiment an iterative process is used to converge on the preferred orientation. The location of the preferred orientation may be marked on the shaft and used to assemble a golf club with the planar oscillation plane in a predetermined orientation. The assembly of the golf club can be done manually—e.g., in a refitting situation—or automatically—e.g., in a new club manufacturing setting.

Abstract: A membrane applied to the ostium of an atrial appendage for blocking blood from entering the atrial appendage which can form blood clots therein is disclosed. The membrane also prevents blood clots in the atrial appendage from escaping therefrom and entering the blood stream which can result in a blocked blood vessel, leading to strokes and heart attacks. The membranes are percutaneously installed in patients experiencing atrial fibrillations and other heart conditions where thrombosis may form in the atrial appendages. A variety of means for securing the membranes in place are disclosed. The membranes may be held in place over the ostium of the atrial appendage or fill the inside of the atrial appendage. The means for holding the membranes in place over the ostium of the atrial appendages include prongs, stents, anchors with tethers or springs, disks with tethers or springs, umbrellas, spiral springs filling the atrial appendages, and adhesives.

Abstract: The preferred orientation, or planar oscillation plane, of a golf club shaft is located by measuring the oscillation of the shaft when a horizontal impulse is applied and from those measurements determining an orientation in which the oscillation would be substantially planar. In a preferred embodiment an iterative process is used to converge on the preferred orientation. The location of the preferred orientation may be marked on the shaft and used to assemble a golf club with the planar oscillation plane in a predetermined orientation. The assembly of the golf club can be done manually—e.g., in a refitting situation—or automatically—e.g., in a new club manufacturing setting.

Abstract: A method of making a golf club includes making a first determination of the location of the effective seam in a shaft and then more precisely locating the seam before attaching a golf club head with the face of the club head facing in a neutral direction.

Abstract: A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedback loop and one for the PLL output—one allows the user to adjust the phase of the output relative to that of the input. Similarly, by providing loadable pre-scale (divide by N), post-scale (divide by K) and feedback-scale (divide by M) counters, one allows the user to adjust the frequency of the output to be M/(NK) times that of the input.

Abstract: The preferred orientation, or planar oscillation plane, of a golf club shaft is located by measuring the oscillation of the shaft when a horizontal impulse is applied and from those measurements determining an orientation in which the oscillation would be substantially planar. In a preferred embodiment an iterative process is used to converge on the preferred orientation. The location of the preferred orientation may be marked on the shaft and used to assemble a golf club with the planar oscillation plane in a predetermined orientation. The assembly of the golf club can be done manually—e.g., in a refitting situation—or automatically—e.g., in a new club manufacturing setting.

Abstract: In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and—to the extent that each such scheme requires a reference voltage—the same reference voltage requirements.

Abstract: A self cleaning bearing assembly for use in a dehydrator washer for particulate solids which comprises a feed reservoir for water and particulate solids and an inclined main screw conveyor having a projecting shaft lower end portion submerged in the reservoir. The bearing assembly comprises a housing having an end cap at one end and an opening at the opposite end in communication with the interior of the feed reservoir. The housing has its longitudinal center line coincident with the main screw conveyor and a stub shaft mounted on the end cap of the bearing assembly also has its axis coincident with that of the main crew conveyor and its shaft. The projecting lower end portion of the main conveyor shaft and the stub shaft are disposed with the stub shaft in radially spaced relationship within the main shaft and a sleeve bearing is disposed in the radial space between the stub shaft and the main shaft.

Abstract: A programmable logic device has embedded random access memory (“RAM”) that can function equally well in either single-port or dual-port operation. The RAM is dual-port RAM whose read address inputs and write address inputs are both connected to a conductor bus via two different sparsely populated programmable interconnection resources. The programmable interconnection resources are arranged so that each pair of corresponding read address and write address inputs can be connected to at least one conductor in common on the conductor bus, allowing the RAM to be configured to mimic a single-port RAM as read address signals and write address signals originating at remote components of the programmable logic device “think” they are being directed to the same address inputs.

Abstract: A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.

Abstract: A wireless communications system that has variable power levels in communications frames may be provided. The wireless communication system may include a plurality of cells that include transmitters for providing communications services to a geographic area. Each cell may be assigned a channel selected from a limited number of available channels. Communications frames may be transmitted in the cells using a plurality of data rates. Each communications frame may include a portion that is to be transmitted at one of the data rates. The power level used for transmitting that portion of a communications frame may be selected (e.g., lowered) to limit at what distances that portion may be properly received. Locations of cells in the geographic area may be partly determined based on the power levels.

Abstract: A wireless local area network that carries mixed traffic of voice and data communications may be provided. The wireless local area network may include an access point and a plurality of remote terminals that are associated with the access point. The access point may be operably coupled to a wireline network. The access point may receive voice and other communications packets from the remote terminals and the wireline network. Some of the packets may be for transmission to the remote terminals. The access point manages which packets to transmit and when to transmit packets. The access point may manage traffic to maintain a fair distribution of packets and to give priority to voice communications over other communications.

Abstract: A color television decoder or other signal processor has a gate controlling the passage of a notch filtered chrominance signal. A filter circuit produces a further chrominance signal which serves as the control signal for the gate.

Abstract: In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and—to the extent that each such scheme requires a reference voltage—the same reference voltage requirements.

Abstract: An LVDS interface for a programmable logic device uses phase-locked loop (“PLL”) circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.