Patents Represented by Attorney Jeffrey L. Brandt
  • Patent number: 4997746
    Abstract: A method is provided for forming a conductive stud and line over a surface, comprising the steps of: forming at least a first layer of material over the region on the surface whereat the conductive stud and line are to be formed; forming a layer of dual image photoresist over the material; exposing the dual image potoresist to radiation so as to form at least first and second regions exhibiting different development characteristics; developing the first region so as to expose a portion of the material; removing the exposed portion of the material so as to define the position of one of the conductive line or stud; developing the second region to expose more of the material; and removing the newly exposed portion of material so as to define the position of the other of the conductive line or stud.
    Type: Grant
    Filed: November 22, 1988
    Date of Patent: March 5, 1991
    Inventors: Nancy A. Greco, Stephen E. Greco
  • Patent number: 4996164
    Abstract: A process of forming a lateral PNP transistor includes the steps of: providing a chip of semiconductor material including an isolated N- device region; implanting N dopant material at a relatively low power and low dosage into a selected implant region of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region; and forming emitter and collector regions in the device region such that an intrinsic base region is defined between the collector and emitter regions in the implant region.
    Type: Grant
    Filed: March 2, 1989
    Date of Patent: February 26, 1991
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Habitz, Chang-Ming Hsieh, Yi-Shiou Huang
  • Patent number: 4991138
    Abstract: A semiconductor memory cell for selectively storing or outputting differential signals responsive to a SELECT signal supplied on a word line includes: a transistor pair having cross-coupled base-collector terminals and emitter terminals connected to a common reference potential; a sensing circuit connected to each of the base-collector terminals in the transistor pair, each of the sensing circuits including (a) a first diode having a cathode connected to the base-collector terminal, (b) a second diode having an anode connected to the anode of the first diode and a cathode connected to the word line, and (c) a circuit connected at the commonly connected anodes of the first and second diodes for amplifying the signal thereat; a writing circuit connected to each of the transistors in the transistor pair, the writing circuit including a transistor having a base connected to the word line and a collector connected to the base-collector terminal; and a circuit for supplying constant current to each of the base-coll
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: February 5, 1991
    Assignee: International Business Machines Corporation
    Inventors: Joseph R. Cavaliere, Alan K. Chan, Michel S. Michail
  • Patent number: 4982257
    Abstract: A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with an extending laterally from another side of the base layer.
    Type: Grant
    Filed: December 19, 1989
    Date of Patent: January 1, 1991
    Assignee: International Business Machines Corporation
    Inventors: Shah Akbar, Patricia L. Kroesen, Seiki Ogura, Nivo Rovedo
  • Patent number: 4975141
    Abstract: A method for detecting the endpoint in an etching process including the steps of: providing a structure to be etched including at least a first layer of material overlying a second layer of material; ablating an aperture in the first layer using a beam of coherent electromagnetic radiation so as to expose a portion of the second layer; exposing the structure to an etchant for etching the second layer; and monitoring the second layer using the ablated aperture so as to detect an endpoint for the etching process.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: December 4, 1990
    Assignee: International Business Machines Corporation
    Inventors: Nancy A. Greco, Joseph P. Nogay
  • Patent number: 4967151
    Abstract: A circuit for testing a differential current switching logic circuit of the type including: a bias potential, two resistors connected to the bias potential, and apparatus responsive to an input signal for sinking a first current through a selected one of the resistors so as to generate first and second differential output signals at the resistors. The circuit includes first, second, and third transistors, each having first and second terminals for conducting a current responsive to a signal applied to a control terminal. Apparatus are provided for supplying a current. The first transistor has its first terminal connected to the current supplying means, and its second terminal connected to a circuit node. The second transistor has its first terminal connected to the circuit node, its second terminal connected to the bias potential, and its control terminal connected to sense the potential at a selected one of the resistors.
    Type: Grant
    Filed: October 11, 1989
    Date of Patent: October 30, 1990
    Assignee: International Business Machines Corporation
    Inventors: Arnold E. Barish, David A. Kiesling, Mark D. Mayo, Walter A. Svarczkopf
  • Patent number: 4965718
    Abstract: In a data processing system of the type including a plurality of processing elements interconnected with each other and with a plurality of memory elements by an interconnection means, a method is provided for accommodating the accessing of a selected memory location in a selected one of the memory elements by at least one requesting processing element to read data stored thereat. The method thereby permits the communication of information between the plurality of processing elements.
    Type: Grant
    Filed: September 29, 1988
    Date of Patent: October 23, 1990
    Assignee: International Business Machines Corporation
    Inventors: David A. George, Bharat D. Rathi
  • Patent number: 4965217
    Abstract: A method of fabricating a lateral transistor is provided, including the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of the device region to define a first transistor region; filling the patterned portion of the device region surrounding the first transistor region with an insulating material to a height generally equal to the surface of with first transistor region; removing portions of the insulating material so as to define a pair of trenches generally bonding opposite sides of the first transistor region; filling the pair of trenches with doped conductive material of opposite conductivity type to the first transistor region; and annealing the semiconductor body whereby to form second and third transistor regions of opposite conductivity type to the first transistor region in the opposing sides of the first transistor region.
    Type: Grant
    Filed: April 13, 1989
    Date of Patent: October 23, 1990
    Assignee: International Business Machines Corporation
    Inventors: Brian H. Desilets, Chang-Ming Hsieh, Louis L. Hsu
  • Patent number: 4962294
    Abstract: A method for causing an open circuit in an electrical conductor is provided, including the steps of: conducting a direct current through the conductor; and applying heat at a selected location on the conductor whereat it is desired to cause the open circuit of the conductor.
    Type: Grant
    Filed: March 14, 1989
    Date of Patent: October 9, 1990
    Assignee: International Business Machines Corporation
    Inventors: Keith F. Beckham, David C. Challener, Arunava Gupta, Joseph M. Harvilchuck, James M. Leas, James R. Lloyd, David C. Long, Horatio Quinones, Krishna Seshan, Morris Shatzkes
  • Patent number: 4960726
    Abstract: A method for manufacturing a BiCMOS device includes providing a semiconductor substrate including first and second electrically isolated device regions. A layer of insulating material is formed over the first device region, and a layer of conductive material is formed conformally over the device. Portions of the conductive layer are removed to leave a base contact on the surface of the second device region and an insulated gate contact over the surface of the first device region. A FET is formed in the first device region having a channel under the insulated gate. A vertical bipolar transistor is formed in the second device region having a base region contacting the base contact.
    Type: Grant
    Filed: October 19, 1989
    Date of Patent: October 2, 1990
    Assignee: International Business Machines Corporation
    Inventors: John S. Lechaton, Dominic J. Schepis
  • Patent number: 4957875
    Abstract: A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposeed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer.
    Type: Grant
    Filed: August 1, 1988
    Date of Patent: September 18, 1990
    Assignee: International Business Machines Corporation
    Inventors: Shah Akbar, Patricia L. Kroesen, Seiki Ogura, Nivo Rovedo
  • Patent number: 4942316
    Abstract: A logic circuit family derived from the conventional 2 level single-ended cascode logic circuit. The basic logic circuit performing a 2--2 OA/AI logic function shown in the attached drawing is given for illustration purposes. It comprises: a logic tree 35 comprised of top and bottom stages 37, 36 dotted at the tree output 38 to perform a determined logic function; the top stage 37 includes a current switch comprised of two input transistors TX34, TX35 connected in a differential amplifier configuration with a reference transistor TX36. The bases of input transistors TX34, TX35 are provided with at least two level shifter devices. Preferably, input level shifter devices are Schottky diodes P31, . . . which move the voltages towards the more positive voltage VPP, to add an AND function on each of these input transistors.
    Type: Grant
    Filed: November 25, 1988
    Date of Patent: July 17, 1990
    Assignee: International Business Machines Corporation
    Inventors: Herve Beranger, Armand Brunin, Bruno Caplier, Jean-Paul Rousseau
  • Patent number: 4916083
    Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled submicron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area.A novel process of forming vertical (e.g.
    Type: Grant
    Filed: March 6, 1989
    Date of Patent: April 10, 1990
    Assignee: International Business Machines Corporation
    Inventors: Michael D. Monkowski, Joseph F. Shepard
  • Patent number: 4915482
    Abstract: A method of modulating light incident to a semiconductor body comprising the steps of: coupling the incident light to the surface plasmon polariton mode at an interface of the semiconductor body; and selectively altering the absorption of the incident light by the semiconductor body so as to decouple the incident light from the surface plasmon polariton mode. The absorption can be selectively altered by establishing a quantum confined optical absorption region within the semiconductor body, and effecting a Stark shift of the quantum confined optical absorption region.
    Type: Grant
    Filed: October 27, 1988
    Date of Patent: April 10, 1990
    Assignee: International Business Machines Corporation
    Inventors: Reuben T. Collins, John R. Kirtley, Thomas N. Theis
  • Patent number: 4914634
    Abstract: A semiconductor memory device including a pair of bit lines (BL, BL) having relatively high stray capacitances (C1, C2), a word line (WL), and a memory cell (MC1) connected to the bit lines and word line for selection by an address signal, and a restore circuit comprising a coupling/equalizing circuit (12) controlled by a BLR clock and a reference voltage generator (51) for quickly restoring the bit lines. The reference voltage generator (51) comprises both static and dynamic current sources. The static current source consists of a small N MOS transistor (N52) operating as a resistor load, while the dynamic current source consists of at least one small P MOS transistor (P'53, . . . ), connected in parallel with the N MOS transistor, and gated with a clock (BCC', . . . ) derived from the BLR clock, so that the P MOS transistor is turned ON during the restore time. An additional N device (N54) may be inserted between the reference line (RL) and ground (GND).
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: April 3, 1990
    Assignee: International Business Machines Corporation
    Inventors: Chekib Akrout, Pierre Coppens, Bernard Denis, Pierre-Yves Urena
  • Patent number: 4901279
    Abstract: A static random access memory cell implemented with metal Schottky field-effect transistors. The cell has first and second branches, each of the branches including: a depletion mode current limiting transistor having a drain connected to a first circuit node; a depletion mode load transistor having a drain connected to the source of the current limiting transistor and a source connected to a second circuit node; an enhancement mode active transistor having a drain connected to the second circuit node and a source connected to a third circuit node; an enhancement mode access transistor having a source connected to the second circuit node and a gate connected to the gate of the current limiting transistor; the gate of the load transistor connected to the second circuit node; the commonly connected gates of the current limiting transistor and the access transistor adapted to receive a word-line signal; and the drain of the access transistor adapted to receive a bit-line signal.
    Type: Grant
    Filed: June 20, 1988
    Date of Patent: February 13, 1990
    Assignee: International Business Machines Corporation
    Inventor: Donald W. Plass
  • Patent number: 4867838
    Abstract: Disclosed is a process for forming a planarized multilevel ship wiring structure. Starting from a substrate having thereon at least a metal stud serving as vertical wiring between two levels of metallization, a quartz layer is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist is applied. The photoresist is converted by silylation process into a silicate having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting to resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazane, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.
    Type: Grant
    Filed: October 17, 1988
    Date of Patent: September 19, 1989
    Assignee: International Business Machines Corporation
    Inventors: Garth A. Brooks, Nancy A. Greco
  • Patent number: 4847670
    Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled sub-micron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area.
    Type: Grant
    Filed: May 11, 1987
    Date of Patent: July 11, 1989
    Assignee: International Business Machines Corporation
    Inventors: Michael D. Monkowski, Joseph F. Shepard
  • Patent number: 4843036
    Abstract: A method of encapsulating an electronic device on a substrate comprises depositing a radiatively curable barrier wall to contain a subsequently deposited encapsulant. Alternatively, an encapsulant comprising a majority of radiatively curable material is used in the absence of a barrier wall.
    Type: Grant
    Filed: June 29, 1987
    Date of Patent: June 27, 1989
    Assignee: Eastman Kodak Company
    Inventors: John D. Schmidt, Martin A. Maurinus
  • Patent number: 4821073
    Abstract: A method is provided for determining the exposure of a photographic negative to be printed in a cropped, enlarged format. The method is performed by defining a region of the negative to be printed, measuring selected density characteristics of the negative in only that region, and determining the exposure based on those measured density characteristics. The method is implemented in an enlarging photographic printer including means for defining the region of the negative to be printed, and means for measuring the selected density characteristics of the negative only in that region. Means are provided for using the selected density characteristics to calculate an exposure for the negative region, and for exposing the negative region onto photographic paper in accordance with the calculated exposure.
    Type: Grant
    Filed: November 19, 1987
    Date of Patent: April 11, 1989
    Assignee: Eastman Kodak Company
    Inventors: Richard J. Backus, Patrick A. Cosgrove